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lg 4572b data s heet mobile display driver ic for a 16m - color wvga tft lcd panel with graphic ram ver sion 1.0. 4 20 1 1 - 04 - 01 1 general description ................................ ................................ ................................ ........ 4 2 features ................................ ................................ ................................ ......................... 5 3 block diagram ................................ ................................ ................................ ................ 6 4 pin description ................................ ................................ ................................ ............... 7 4.1 pin list ................................ ................................ ................................ ............................. 7 4.2 pin assignment ................................ ................................ ................................ ................ 11 4.3 bump coordinates ................................ ................................ ................................ ............ 12 4.4 bump arrangement ................................ ................................ ................................ .......... 24 5 functional description ................................ ................................ ................................ . 25 5.1 mipi dbi type - a ................................ ................................ ................................ .............. 25 5.1.1 write cycle sequence ................................ ................................ ............................... 25 5.1.2 read cycle sequence ................................ ................................ ............................... 26 5.2 mipi dbi type - b ................................ ................................ ................................ .............. 27 5.2.1 write cycle sequence ................................ ................................ ............................... 27 5.2.2 read cycle sequence ................................ ................................ ............................... 28 5.2.3 interface color codin g for dbi type a and b ................................ ............................. 30 5.2.4 interface color coding for gram data write ................................ .............................. 38 5.3 mipi dbi type c ................................ ................................ ................................ .............. 41 5.3.1 write cycle sequence ................................ ................................ ............................... 41 5.3.2 read cycle sequence ................................ ................................ ............................... 41 5.3.3 break and pause of sequences ................................ ................................ .................. 42 5.3.4 data transfer break ................................ ................................ ................................ . 42 5.4 mipi dpi - 2 ................................ ................................ ................................ ....................... 44 5.4.1 interface signals ................................ ................................ ................................ ...... 44 5.4.2 interface color coding ................................ ................................ .............................. 44 5.4.3 interface timing parameter ................................ ................................ ...................... 45 5.5 spi ( serial peripheral interface) ................................ ................................ ........................ 47 5.5.1 write cycle sequence ................................ ................................ ............................... 47 5.6 mipi dsi ................................ ................................ ................................ .......................... 49 5.6.1 dsi layer definitions ................................ ................................ ................................ 50 5.6.2 command and video modes ................................ ................................ ...................... 51 5.6.3 dsi physical layer (d - phy) ................................ ................................ ....................... 52 5.6.4 interconnect ................................ ................................ ................................ ............ 52 5.6.5 d - phy signal voltage levels & speed ................................ ................................ ........ 53 5.6.6 high speed data transmission with d - phy ................................ ................................ 54 5.6.7 low power data transmission with d - phy ................................ ................................ . 54 5.6.8 dsi protocol ................................ ................................ ................................ ............. 55 5.7 mddi ................................ ................................ ................................ ............................... 64 5.7.1 mddi data and stb ................................ ................................ ................................ . 64 5.7.2 mddi packet ................................ ................................ ................................ ............ 66 5.7.3 write and read sequences with mddi packet ................................ ............................ 68 5.7.4 tearing - less display ................................ ................................ ................................ . 70 5.7.5 hibernation and wakeup ................................ ................................ ........................... 71 5.7.6 mddi operation modes ................................ ................................ ............................. 75 5.8 backlight control function ................................ ................................ ................................ 78
LG4572B ver. 1.0. 4 lge confidential 2 5.8.1 cabc ( content ada ptive brightness control ) ................................ .............................. 78 5.8.2 brightness control block and cabc block ................................ ................................ ... 79 5.9 lcd power supply circuit ................................ ................................ ................................ .. 82 5.9.1 voltage setting pattern diagram ................................ ................................ ............... 82 5.9.2 power on/ off sequence ................................ ................................ ............................ 83 5.9.3 display on sequence ................................ ................................ ................................ 84 5.9.4 sleep in, out sequence ................................ ................................ ............................ 85 5.9.5 dstb in, dstb out , display on sequence ................................ ................................ 86 5.10 gamma correction function ................................ ................................ .............................. 87 5.10.1 grayscale generation unit configuration ................................ ................................ .... 88 5.10.2 gamma correction register ................................ ................................ ...................... 89 5.10.3 ladder resistors and 8 - to - 1 selector ................................ ................................ ......... 91 5.11 oscillator ................................ ................................ ................................ ......................... 95 5.12 otp control ................................ ................................ ................................ ..................... 96 5.13 eeprom control ................................ ................................ ................................ ............. 101 6 commands ................................ ................................ ................................ ................. 103 6.1 command list ................................ ................................ ................................ ................ 103 6.2 command description ................................ ................................ ................................ ..... 113 6.2.1 00h C no operation ................................ ................................ ................................ 113 6.2.2 01h C software reset ................................ ................................ ............................. 114 6.2.3 0ah C read display power mode ................................ ................................ ............. 115 6.2.4 0bh C read display madctl ................................ ................................ ................... 117 6.2.5 0ch C read display pixel format ................................ ................................ ............. 119 6.2.6 0dh C read display image mode ................................ ................................ ............. 121 6.2.7 0dh C read display image mode ................................ ................................ ............. 122 6.2.8 0eh C read display signal mode ................................ ................................ .............. 123 6.2.9 10h C sleep in ................................ ................................ ................................ ....... 125 6.2.10 11h C sleep out ................................ ................................ ................................ ..... 126 6.2.11 12h C partial mode on ................................ ................................ ............................ 127 6.2.12 13h C normal display mode on ................................ ................................ ............... 128 6.2.13 20h C disp lay inversion off ................................ ................................ ..................... 129 6.2.14 21h C display inversion on ................................ ................................ ..................... 131 6.2.15 28h C display off ................................ ................................ ................................ ... 133 6.2.16 29h C display on ................................ ................................ ................................ .... 135 6.2.17 2ah C column address s et ................................ ................................ ...................... 1 37 6.2.18 2bh C page address set ................................ ................................ .......................... 139 6.2.19 2ch C write memory start ................................ ................................ ....................... 141 6.2.20 2eh C read memory start ................................ ................................ ....................... 143 6.2.21 30h C partial area definition ................................ ................................ .................... 145 6.2.22 34h C tearing effect line off ................................ ................................ .................. 148 6.2.23 35h C tearing effect line on ................................ ................................ ................... 149 6.2.24 36h C memory access control ................................ ................................ ................. 151 6.2.25 3ah C interface pixel format ................................ ................................ ................... 157 6.2.26 3ch C writ e memory continue ................................ ................................ ................. 159 6.2.27 3eh C read memory continue ................................ ................................ ................. 161 6.2.28 44h C set tear scan line ................................ ................................ ......................... 163 6.2.29 45h C get scan line ................................ ................................ ................................ 164 6.2.30 51h C write display brightness ................................ ................................ ................ 166 6.2.31 52h C read display brightness value ................................ ................................ ....... 167 6.2.32 53h C write control display ................................ ................................ .................... 169 6.2.33 54h C read control display ................................ ................................ ..................... 171 6.2.34 55h C write content adaptive brightness control ................................ ..................... 172 6.2.35 56h C read content adaptive brightness control ................................ ...................... 173 6.2.36 5eh C wr ite cabc minimum brightness ................................ ................................ .... 174 6.2.37 5fh C read cabc minimum brightness ................................ ................................ .... 175 6.2.38 a1h C read ddb start ................................ ................................ ............................ 176
LG4572B ver. 1.0. 4 lge confidential 3 6.2.39 b1h C rgb interfac e setting ................................ ................................ ................... 177 6.2.40 b2h C panel characteristics setting ................................ ................................ .......... 179 6.2.41 b3h C panel drive setting ................................ ................................ ....................... 181 6.2.42 b4h C display mode control ................................ ................................ .................... 182 6.2.43 b5h C displa y control 1 ................................ ................................ .......................... 183 6.2.44 b6h C display control 2 ................................ ................................ .......................... 187 6.2.45 b7h C display control 3 ................................ ................................ .......................... 205 6.2.46 c0h C internal oscillator setting ................................ ................................ .............. 207 6.2.47 c1h C power control 1 ................................ ................................ ............................ 209 6.2.48 c2h C power control 2 ................................ ................................ ............................ 210 6.2.49 c3h C power control 3 ................................ ................................ ............................ 212 6.2.50 c4h C power control 4 ................................ ................................ ............................ 217 6.2.51 c5h C power control 5 ................................ ................................ ............................ 221 6.2.52 c6h C power contro l 6 ................................ ................................ ............................ 223 6.2.53 c7h C offset cancelling control ................................ ................................ ............... 225 6.2.54 c8h C backlight control ................................ ................................ .......................... 227 6.2.55 d0h C positive gamma curve for red ................................ ................................ ...... 228 6.2.56 d1h C negative gamma curve for red ................................ ................................ .... 229 6.2.57 d2h C positive gamma curve for green ................................ ................................ ... 230 6.2.58 d3h C negative gamma curve for green ................................ ................................ . 231 6.2.59 d4h C positive gamma curve for blue ................................ ................................ ..... 232 6.2.60 d5h C negative gamma curve for blue ................................ ................................ .... 233 6.2.61 e0h C mddi control ................................ ................................ ............................... 234 6.2.62 e1h C frame memory control ................................ ................................ .................. 236 6.2.63 e2h C eeprom read control ................................ ................................ .............. 237 6.2.64 f0h C test register 1 ................................ ................................ ............................. 238 6.2.65 f1h C test registe r 2 ................................ ................................ ............................. 239 6.2.66 f8h C otp 1 ................................ ................................ ................................ ........... 240 6.2.67 f9h C otp 2 ................................ ................................ ................................ ........... 241 6.2.68 fah C otp 3 ................................ ................................ ................................ .......... 242 7 electrical characteristics ................................ ................................ ............................ 243 7.1 absolute maximum ratings ................................ ................................ ............................. 243 7.2 power supply specifications ................................ ................................ ............................ 244 7.3 dc characteristics ................................ ................................ ................................ .......... 245 7.4 ac characteristics ................................ ................................ ................................ ........... 246 7.4.1 mipi hs receiver characteristics ................................ ................................ ............. 246 7.4.2 mipi lp receiver characteristic s ................................ ................................ .............. 248 7.4.3 mipi lp transmitter characteristics ................................ ................................ ......... 249 7.4.4 mddi transmitter characteristics ................................ ................................ ............ 251 7.4.5 mddi receiver characteristics ................................ ................................ ................. 252 7.4.6 interconnect network requirement for mddi ................................ ........................... 254 7.4.7 serial peripheral interface characteristics ................................ ................................ 258 7.4.8 reset timing characteristics ................................ ................................ ................... 258 7.4.9 rgb interface timing characteristics ................................ ................................ ....... 259 7.4.10 68 - system bus interface timing characteristics (18/16 - bit bus) ................................ 259 7.4.11 80 - system bus interface timing characteristics (18/16 - bit bus) ................................ 260 8 reference applications ................................ ................................ .............................. 262 8.1 configuration of power su pply circuit ................................ ................................ .............. 262 9 history of revision ................................ ................................ ................................ ..... 267
LG4572B ver. 1.0. 4 lge confidential 4 1 general description the lg 4572b is a 16m color one - chip contro ller driver lsi for a - si tft liquid crystal display with supporting various resolution s of max. 480rgb x 864 dots gip 1 panel. the driver supports mipi 2 dbi 3 type b (8 - bit). and it supports dpi 4 (vsync, hsync, pclk, de, and db[23:0]) a s for moving picture interface. the driver also supports mipi dsi 5 with d - phy interface fo r high - speed and low power transmission in both directions with low emi noise . mddi 6 is also supported by lg 4572b . the lg 4572b supports dot inversion for higher image quality and moving flicker free image realizations with low power driving. the lg 4572b also supports blu 7 control functionality by analyzing the display data properties and it helps to get lower power consumptions without image losses. the lg 4572b can o perate with low i/o interface power supply down to 1. 65 v, with an incorporated voltage follower circuit to generate voltage levels for driving an lcd. the driver also supports function s such as 8 - color displays and shut down. and t hese features make the lg 4572b an ideal lcd driver for medium or small sized portable products supporting www full browsers such as smart phones or pdas, where long battery life is a major concern. not ice 1 : the mddi interface supported by the lg 4572b is designed and produced b ased on the licensing of technology from qualcom. the mddi interface can be adopted in the module, which incorporates a qualcom ? s cdma asic. any claims, including, but not limited to the third party ? s right to use the mddi interface for industrial purposes shall not be accepted by lge. notice 2 : the information contained here is subject to change without notice. the information contained here is presented only as a guide for the applications of our products. lg is not responsible for any infringement of patents or other rights of third parties that may result from the use of lg products, and the use of lg products is without any right to indemnification, or defense to any allegation of, infringement of intellectual property rights of others. no license i s granted by implication of otherwise under any patent or patent rights of lg or others and by accepting possession of any lg product user acknowledges that no rights to the patents of lg or others are transferred with such product and that a separate lice nse from lg or others may be necessary. these lg products are intended for the exclusive use of general electronic equipment (i.e.: office equipment, communication equipment, measuring equipment, domestic electrification, etc.) . please make sure that y ou consult us before you use any lg products or equipment that require special uses or exceptional applications and any equipment that may impact the welfare of human life (i.e.: atomic energy control, airplane, spaceship, traffic signal, combustion contro l, all types of safety devices, etc.). lg is not liable for any damage that may occur by the improper use of the equipment without consulting lg prior to its use. purchased lg i2c components. under the license of philips i2c patent rights must be used onl y for an i2c system C provided that the system conforms to the i2c standard specification as defined by philips. 1 gip C gate in panel 2 mipi C mobile indu strial processor interface 3 dbi C display bus interface 4 dpi C display pixel interface 5 dsi C display serial interface 6 mddi C mobile display digital interface 7 blu C backlight unit
LG4572B ver. 1.0. 4 lge confidential 5 2 features ? a single - chip controller driver incorporating a gip gate circuit and a power supply circuit for maximum 480rgb x 864 dots graphics d isplay on a - si tft panel in 16m colors. it supports 4n row resolutions of gate outputs in panel. in case of 854 row resolution, it is not divided by 4. but 856 row resolution could be chosen to support 854 row resolution by using dummy 2 ro w s. ? system inter face frame buffer mode - mipi dbi type b (8 - , 9 - , 16 - , 18 - , 24bit). - mipi dsi with d - phy (dsi : version 1.01.00 C 21 february 2008, d - phy : version 0.90.00 C 8 october 2007) - mddi (mobile display digital interface) v1.2 fr ame buffer bypass mode - mipi dpi (vsy nc, hsync, pclk, de, and db[23:0]) - mipi dsi with d - phy (dsi: version 1.01.00 C 21 february 2008, d - phy: version 0.90.00 C 8 october 2007) - spi ? in frame buffer mode, arbitrary number of source channels can be chosen, which is less than 480rgb, by using wind ow mode . the unused source outputs are made floating. but, in frame buffer bypass mode, 240rgb, 320rgb, 360rgb and 480rgb source channels could be chosen for some applications. and the unused sourc e outputs are made floating . ? window address function to specify a rectangular area in the internal ram to write data. ? abundant color display and drawing functions - programmable gamma correction function for 16m color display - partial display function ? n - line dot inversion and column inversion, where n can be 1,2, and 3. ? internal r, g, b independent gamma reference voltages generation function ? contents adaptive blu control function for optimal power consumption ? cst structure is only supported. ? reversible source output shift direction by internal register setting ? in ternal level shifter for gip gate controls ? internal power supply generations. the dc - dc charge pumping circuitry and pfm booster with external inductor and external nmos transistors are used. ? internal nvm (nonvolatile memory) for vcom level adjustment : 7 bits x 4 ? low power consumption architecture - standby function (logic vdd is alived) - deep standby function (logic vdd is dead to be 0 - volt) ? input power supply voltage ranges - interface power supply: iovcc = 1.65 to 3.3v - power supply for vdd generation: vcc = 2.6 to 3.3v but make sure that internally - generated logic voltage (vdd) will not exceed 1. 70 v - analog power supply : vci = 2.6 to 3.3v but make sure that max. voltage difference of vgh and lvgl will not exceed 29.5 v ? generated power supply voltage ran ges - logic vdd voltage : 1. 4 0 to 1. 7 0 v - source driver power supply positive voltage : ddvdh = 4.5 to 5.5v - source driver power supply negative voltage : ddvdl= - 4.0 to - 5.0v - gate on voltage : vgh - gate off voltage : vgl - gip most negative reference voltage : l vgl (vgl - vci) - vgh - lvgl < 29.5 v, vgh - gnd < 1 5 v (absolute maximum) - vcom voltage : 0v, - 0.5v ~ - 3.5v
LG4572B ver. 1.0. 4 lge confidential 6 3 block diagram figure 1 . lg 4572b block diagram g i p d r i v e r c i r c u i t s s 1 s 1 4 4 0 s o u r c e d r i v e c i r c u i t g a m m a r g a m m a g g a m m a b f w _ l , b w _ l , g p w r 1 _ l , g p w r 2 _ l , g c l k 1 _ l , g c l k 2 _ l , g c l k 3 _ l , g c l k 4 _ l , g v s t 1 _ r , g v s t 2 _ l , f w _ r , b w _ r , g p w r 1 _ r , g p w r 2 _ r , g c l k 1 _ r , g c l k 2 _ r , g c l k 3 _ r , g c l k 4 _ r , g v s t 1 _ r , g v s t 2 _ r , p o w e r g e n e r a t i n g c i r c u i t s c 2 1 p / c 2 1 n c 2 2 p / c 2 2 n v g h d d v d l v g l c 2 3 p / c 2 3 n v d d o u t v d d i m [ 3 : 0 ] n c s n w r _ e _ s c k n r d _ r n w s d i d b [ 2 3 : 0 ] h s y n c v s y n c _ t e p c l k d e n r e s e t d n c s y s t e m i n t e r f a c e t i m i n g c o n t r o l l e r c 2 4 p / c 2 4 n m i p i i n t e r f a c e d a t a 1 n / d a t a 1 p c l k p / c l k n d a t a 0 n / d a t a 0 p l v g l c 4 1 p / c 4 1 n v g s v g s _ n b l u _ p w m c r e g b l u _ e n v b i a s i o v c c v c c v c i g n d l s w s d o d d v d h v c l c 3 1 p / c 3 1 n v r e g 1 o u t v r e g 2 o u t v c o m r e g u l a t o r s b r i g h t n e s s c o n t r o l v 1 2 _ s e l v p p g r a p h i c r a m 9 , 9 5 3 , 2 8 0 b i t s w r i t e r e a d
LG4572B ver. 1.0. 4 lge confidential 7 4 pin description 4.1 pin list name # p ins i/o connected to function im 3 im2 im1 im0(id) 4 i mpu mpu interface mode selection signal im[3: 0 ] reg ister access pixel data 0000 mipi dbi type a (m68) 16 0001 8 1000 18/24 1001 9 0010 mipi dbi type b (i80) 16 0011 8 1010 18/24 1011 9 0100 mipi dbi type c mipi dpi 0101 mipi dsi (only for phy 2 lane is available) 110x spi mipi dpi 011 0 mipi dsi with phy 1 lane 0111 mipi dsi with phy 2 lane 111x mddi n reset 1 i mpu or external rc circuit reset pin (active low) be sure to execute a power - on reset aft er supplying power. n cs 1 i mpu chip select (active low) this pin should be connected to iovcc when mipi or mddi i/fs are used. d n c 1 i mpu data (1) or command (0) select db[ 23 :0] 24 i/o mpu parallel data bus unused pins must be fixed either iovcc or g nd level. nrd_rnw 1 i mpu (i80 interface) n rd - read strobe (active low) (m68 interface) r n w - read (1) or write (0) select n wr _e_ sck 1 i mpu (i80 interface) n wr - write strobe (active low) (m68 interface) e - enable (spi interface) sck - serial clock s di 1 i mpu (spi interface) serial data input sdo 1 o mpu (spi interface) serial data output pclk 1 i mpu pixel clock vsync _te 1 i /o mpu frame synchronization signal. it is vsync input pin when mipi dpi pixel data interface mode, but it turns out to be output pin in other modes for te (tearing effect) signaling. hsync 1 i mpu line synchronization signa l. it is vsync input pin when dpi pixel data interface mode. fix to either iovcc or gnd level when not in use.
LG4572B ver. 1.0. 4 lge confidential 8 name # p ins i/o connected to function de 1 i mpu data enable signal in rgb int erface mode. fix to either iovcc or gnd level when not in use. clkn, clkp 2 i mpu d ifferential clock or strobe pair for mipi and/or mddi high speed serial interface. i f mipi and/or mddi were not used, they should be connected to gnd. in mddi interface mo de, preci si on 100ohm resistor should be connected between clkn and clkp. data 0n, data1n, data 0p, data1p 4 i/o mpu d ifferential data pairs for mipi and/or high seep serial interface. i f mipi and/or mddi were not used, they should be connected to gnd. in mddi interface mode, preci si on 100ohm resistors should be connected between datan0 and datap0, and between datan1 and datap1. v 12_sel 1 i iovcc or gnd when vci<2.9v, then v12_sel=gnd is recommended. when vci>2.9v, then v12_sel=iovcc is recommended. this pin is only for mipi interface. this pin should not be floating in any case. test1 1 i gnd test pin fix to gnd level in normal operation mode test2 1 i gnd test pin fix to gnd level in normal operation mode blu_en 1 o blu blu enable (active h igh ) if not used, leave this pin open blu_pwm 1 o blu blu pwm signal (depends on pwmp in c8h register: 0 ? ? the source driver?s lcd output unit
LG4572B ver. 1.0. 4 lge confidential 9 name # p ins i/o connected to function ddvdh 1 i power supply for the source driver?s lcd output unit 1 i power supply power supply to the interface pins: iovcc = 1.65 to 3. 3 v. vcc 1 i power supply power supply to generate the internal logic power supply vdd. vcc = 2.6 to 3. 3 v vdd 1 i power supply generated power supply for the internal logic . vddout 1 i/o stabilizing capacitor and vdd internal logic regulator output. connect vdd to a stabilizing capacitor. vss 1 i power supply vss =0. vci 1 i power supply supply voltag e to the analog circuit. connect to an external power supply of 2.6 to 3. 3 v. vcom 1 o tft panel common electrode supply voltage to the common electrode of tft panel. vcomr 1 i variable resistor or open reference level to generate the vcom level with an externally connected variable resistor. the vreg2out voltage could be a reference to generate vcomr. leave it open when not in use. creg 1 o stabilizing c apacitor regulator output that needs to be connected with stabilizing capacitor for mipi block. lea ve it open when mipi were not used. gnd_sh 1 i gnd gnd. this is for shielding differential clock and data signals for mipi dsi or mddi . lsw 1 o gate terminal of external switching tr. external switching transistor?s gate on/off control signal
LG4572B ver. 1.0. 4 lge confidential 10 name # p ins i/o connected to function c31n, c31p 2 i/o step - up capacitor connect step - up capacitor to generate ddvdl when charge pumping method is used instead of diode - inverti n g. when ddvdh is supplied external ly , this capacitor is necessary to generate ddvdl. leave them open when not in use. c41n, c41p 2 i/o step - up capacitor connect step - up capacitor to generate lvgl only for h - type panel. leave them open when not in use. vpp 1 i 7.75v power supply for internal otp programming to adjust vc om level. leave this pin open except when otp programming. gout_test1, gout_test2 2 dummy dummy pads only with bump dum_von 1 dummy dummy pad only with bump dum_data1, dum_data2 2 dummy dummy pads only with bump they are shorted together. dum_gout 1 dummy dummy pads only with bump osc1,2,3 3 i/o external resistor or capacitor reserved pins for external r and c combined oscillation frequencies. they can be used to get higher and more stable oscillation frequencies . rsda 1 i/o external resistor to iovcc around 10kohm resistor can be connected in - between rsda and iovcc when i2c interface is activated by setting eeprom=1. rscl 1 i/o reading clock to fetch register values from external eeprom. it should not exceed 400khz at maximum.
LG4572B ver. 1.0. 4 lge confidential 11 4.2 pin assign ment f w _ l b w _ l g p w r 1 _ l g p w r 2 _ l g c l k 4 _ l g c l k 4 _ l g c l k 3 _ l g c l k 3 _ l g c l k 2 _ l g c l k 2 _ l g v s t 1 _ l g v s t 2 _ l v g l v g l v g l v b i a s l v g l l v g l l v g l g o u t _ t e s t 1 v c o m v c o m v c o m d u m _ v o n d u m _ d a t a 1 d u m _ d a t a 2 d u m _ g o u t v g l v g l v g l l v g l l v g l l v g l l v g l l v g l v c o m v c o m v c o m v c o m c 4 1 p c 4 1 p c 4 1 p c 4 1 n c 4 1 n c 4 1 n v g h v g h v g h v g h v g h v g h c 2 1 n c 2 1 n c 2 1 n c 2 1 p c 2 1 p c 2 1 p c 2 3 n c 2 3 n c 2 3 n c 2 3 n c 2 3 p c 2 3 p c 2 3 p c 2 3 p c 2 2 p c 2 2 p c 2 2 p c 2 2 p c 2 2 n c 2 2 n c 2 2 n c 2 2 n c 2 4 n c 2 4 n c 2 4 n c 2 4 n c 2 4 p c 2 4 p c 2 4 p c 2 4 p v p p v p p v c l v c l v c l v c l v c l v c i v c i v c i v c i v c i v c i l s w l s w d d v d h d d v d h d d v d h d d v d h d d v d h d d v d h v s s v s s v s s v s s v s s v s s v s s v s s v d d v d d s 1 4 3 3 s 1 4 3 4 s 1 4 3 5 s 1 4 3 6 s 1 4 3 7 s 1 4 3 8 s 1 4 3 9 s 1 4 4 0 l g 4 5 7 2 s t a g g e r e d a r r a n g e m e n t - l e f t s i d e h a l f - ( b u m p v i e w ) ( 1 - a ) n o . 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 1 0 1 1 0 2 1 0 3 1 0 4 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 c 2 1 n c 2 1 p v s s v s s v s s v s s v s s v s s v d d v d d v d d v d d v d d v d d v d d v d d v d d o u t v d d o u t v d d o u t v d d o u t v d d o u t v r e g 1 o u t v g s d d v d h d d v d h d d v d h d d v d h d d v d h d d v d h d d v d h d d v d h c 3 1 p c 3 1 p c 3 1 p c 3 1 p c 3 1 n c 3 1 n c 3 1 n c 3 1 n d d v d l d d v d l d d v d l d d v d l d d v d l d d v d l d d v d l v c i v c i v c i v c i v c i v c i v g h v g h v g h v g h v c o m v c o m v c o m v c o m l v g l l v g l l v g l l v g l d u m _ g o u t v c o m r d u m _ v o n v c o m v c o m v c o m d u m m y g o u t _ t e s t 2 l v g l l v g l l v g l v b i a s v g l v g l v g l v g l g v s t 2 _ l g v s t 1 _ l g c l k 1 _ l g c l k 1 _ l g c l k 2 _ l g c l k 2 _ l s 3 s 4 s 5 s 6 x y ( 1 - b ) n o . 3 1 2 n o . 1 6 3 n o . 1 6 2 x y l g 4 5 7 2 s t a g g e r e d a r r a n g e m e n t - r i g h t s i d e h a l f - ( b u m p v i e w ) c l k n c l k n c l k p c l k p c l k p v s s _ s h 4 c r e g c r e g v c c v c c v c c v c c v c c v s s v s s v s s v s s v s s v s s v s s v s s v s s c l k n ? c h i p s i z e : 2 2 . 3 5 x 1 . 4 5 m m 2 ( w i t h s e a l r i n g b u t w i t h o u t s c r i b e l i n e ) ? c h i p t h i c k n e s s : 2 5 0 u m ? p a d c o o r d i n a t i o n : p a d c e n t e r ? c o o r d i n a t i o n o r i g i n : c h i p c e n t e r ? a u b u m p s i z e ( 1 ) 5 0 . 0 0 u m x 8 0 . 0 0 u m n o . 1 C n o . 3 1 2 ( 2 ) 1 5 . 0 u m x 1 0 0 . 0 u m n o . 3 1 3 C n o . 1 7 5 6 ? a u b u m p p i t c h : 1 5 u m f o r s t a g g e r e d p a d s a n d 7 0 u m f o r i n - l i n e p a d s ? a u b u m p h e i g h t : 1 2 u m ( t y p . ) ? n o . i n t h e f i g u r e c o r r e s p o n d s t o n o . i n t h e p a d c o o r d i n a t i o n t a b l e ? a l i g n m e n t m a r k 1 2 0 u m 6 0 u m 6 0 u m 1 2 0 u m 3 0 3 0 3 0 3 0 3 0 3 0 1 5 1 5 1 5 1 5 n o . 1 0 3 4 n o . 3 1 3 n o . 1 7 5 6 n o . 1 0 5 7 v d d v d d v d d v d d 1 1 7 1 1 8 1 1 9 1 2 0 g c l k 3 _ l g c l k 3 _ l g c l k 4 _ l g c l k 4 _ l b w _ r 1 3 1 1 3 2 1 3 3 1 3 4 1 3 5 1 3 6 1 3 7 1 3 8 1 3 9 1 4 0 1 4 1 1 4 2 1 4 3 1 4 4 1 4 5 1 4 6 1 4 7 1 4 8 i o v c c i o v c c i m 0 i m 1 i m 2 i m 3 n r e s e t v s s _ d u m 1 5 0 1 5 1 1 5 2 i o v c c 1 4 9 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 1 2 9 1 3 0 1 7 3 1 7 4 1 7 5 1 7 6 1 7 7 1 7 8 1 7 9 1 8 0 1 8 1 1 8 2 1 8 3 1 8 4 1 8 5 1 8 6 1 8 7 1 8 8 1 8 9 1 9 0 1 9 1 1 9 2 1 9 3 1 9 4 1 9 5 1 9 6 1 9 7 1 9 8 1 9 9 2 0 0 2 0 1 2 0 2 2 0 3 2 0 4 2 0 5 2 0 6 2 0 7 2 0 8 2 0 9 2 1 0 2 1 1 2 1 2 2 1 3 2 1 4 2 1 5 2 1 6 2 1 7 2 1 8 2 1 9 2 2 0 2 2 1 2 2 2 2 2 3 2 2 4 2 2 5 2 2 6 2 2 7 2 2 8 2 2 9 2 3 0 2 3 1 2 3 2 1 6 3 1 6 4 1 6 5 1 6 6 1 6 7 1 6 8 1 6 9 1 7 0 1 7 1 1 7 2 2 3 3 2 3 4 2 3 5 2 3 6 2 3 7 2 3 8 2 3 9 2 4 0 2 7 3 2 7 4 2 7 5 2 7 6 2 7 7 2 7 8 2 7 9 2 8 0 2 8 1 2 8 2 2 8 3 2 8 4 2 8 5 2 8 6 2 8 7 2 8 8 2 8 9 2 9 0 2 9 1 2 9 2 2 9 3 2 9 4 2 9 5 2 9 6 2 9 7 2 9 8 2 9 9 3 0 0 3 0 1 3 0 2 3 0 3 3 0 4 3 0 5 3 0 6 3 0 7 3 0 8 3 0 9 3 1 0 3 1 1 3 1 2 2 4 1 2 4 2 2 4 3 2 4 4 2 4 5 2 4 6 2 4 7 2 4 8 2 5 0 2 5 1 2 5 2 2 5 3 2 5 4 2 5 5 2 5 6 2 5 7 2 5 8 2 5 9 2 6 0 2 6 1 2 6 2 2 6 3 2 6 4 2 6 5 2 6 6 2 6 7 2 6 8 2 6 9 2 7 0 2 7 1 2 7 2 2 4 9 v 1 2 _ s e l d u m m y o s c 1 o s c 2 o s c 3 v s s _ s h 1 d a t a 0 n d a t a 0 n d a t a 0 n d a t a 0 p d a t a 0 p d a t a 0 p v s s _ s h 2 d a t a 1 n d a t a 1 n d a t a 1 n d a t a 1 p d a t a 1 p d a t a 1 p v s s _ s h 3 n w r _ e _ s c k d n c n c s r s c l s d i s d o v s y n c _ t e h s y n c d e p c l k s 1 s 2 d u m m y d u m m y s 7 2 1 s 7 2 2 s 7 2 3 s 7 2 4 s 7 2 5 s 7 2 6 d u m m y d u m m y s 7 1 7 s 7 1 8 s 7 1 9 s 7 2 0 s 7 1 6 d u m m y g c l k 1 _ l g c l k 1 _ l i o v c c i o v c c b l u _ p w m b l u _ e n t e s t 1 t e s t 2 f w _ r d u m m y g p w r 2 _ l g p w r 1 _ l d u m m y v r e g 2 o u t v g s _ n d b < 1 7 > d b < 1 6 > d b < 1 5 > d b < 1 4 > d b < 1 3 > d b < 1 2 > d b < 1 1 > d b < 1 0 > d b < 9 > d b < 8 > d b < 2 3 > d b < 2 2 > d b < 2 1 > d b < 2 0 > d b < 1 9 > d b < 1 8 > 1 5 7 1 5 8 1 5 9 1 6 0 1 6 1 1 6 2 d b < 3 > d b < 2 > d b < 1 > d b < 0 > r s d a n r d _ r n w 1 5 3 1 5 4 1 5 5 1 5 6 d b < 7 > d b < 6 > d b < 5 > d b < 4 > d u m m y d u m m y d u m m y d u m m y d u m m y x y -11060 600 11060 600 alignment mark 1-a 1-b
LG4572B ver. 1.0. 4 lge confidential 12 4.3 bump coordinates no. name x y 1 dummy - 10885 - 672 2 fw_l - 10815 - 672 3 bw_l - 10745 - 672 4 gpwr1_l - 10675 - 672 5 gpwr2_l - 10605 - 672 6 gclk4_l - 10535 - 672 7 gclk4_l - 10465 - 672 8 gclk3_l - 10395 - 672 9 gclk3_l - 103 25 - 672 10 gclk2_l - 10255 - 672 11 gclk2_l - 10185 - 672 12 gclk1_l - 10115 - 672 13 gclk1_l - 10045 - 672 14 gvst1_l - 9975 - 672 15 gvst2_l - 9905 - 672 16 vgl - 9835 - 672 17 vgl - 9765 - 672 18 vgl - 9695 - 672 19 vbias - 9625 - 672 20 lvgl - 9555 - 672 21 lvgl - 9485 - 672 22 lvgl - 9415 - 672 23 gout_test1 - 9345 - 672 24 vcom - 9275 - 672 25 vcom - 9205 - 672 26 vcom - 9135 - 672 27 dum_von - 9065 - 672 28 dum_data1 - 8995 - 672 29 dum_data2 - 8925 - 672 30 dum_gout - 8855 - 672 31 vgl - 8785 - 672 32 vgl - 8715 - 672 33 vgl - 8645 - 672 34 lvgl - 8575 - 672 35 lvgl - 8505 - 672 36 lvgl - 8435 - 672 37 lvgl - 8365 - 672 38 lvgl - 8295 - 672 39 vcom - 8225 - 672 40 vcom - 8155 - 672 41 vcom - 8085 - 672 42 vcom - 8015 - 672 43 c41p - 7945 - 672 44 c41p - 7875 - 672 45 c41p - 7805 - 672 46 c41n - 7735 - 672 47 c41n - 7665 - 672 48 c41n - 7595 - 672 49 vgh - 7525 - 672 50 vgh - 7455 - 672 no. name x y 51 vgh - 7385 - 672 52 vgh - 7315 - 672 53 vgh - 7245 - 672 54 vgh - 7175 - 672 55 c21n - 7105 - 672 56 c21n - 7035 - 672 57 c21n - 6965 - 672 58 c21n - 6895 - 672 5 9 c21p - 6825 - 672 60 c21p - 6755 - 672 61 c21p - 6685 - 672 62 c21p - 6615 - 672 63 c23n - 6545 - 672 64 c23n - 6475 - 672 65 c23n - 6405 - 672 66 c23n - 6335 - 672 67 c23p - 6265 - 672 68 c23p - 6195 - 672 69 c23p - 6125 - 672 70 c23p - 6055 - 672 71 c22p - 5985 - 67 2 72 c22p - 5915 - 672 73 c22p - 5845 - 672 74 c22p - 5775 - 672 75 c22n - 5705 - 672 76 c22n - 5635 - 672 77 c22n - 5565 - 672 78 c22n - 5495 - 672 79 c24n - 5425 - 672 80 c24n - 5355 - 672 81 c24n - 5285 - 672 82 c24n - 5215 - 672 83 c24p - 5145 - 672 84 c24p - 5075 - 672 85 c24p - 5005 - 672 86 c24p - 4935 - 672 87 vpp - 4865 - 672 88 vpp - 4795 - 672 89 vcl - 4725 - 672 90 vcl - 4655 - 672 91 vcl - 4585 - 672 92 vcl - 4515 - 672 93 vcl - 4445 - 672 94 vci - 4375 - 672 95 vci - 4305 - 672 96 vci - 4235 - 672 97 vci - 4165 - 672 98 vci - 4095 - 672 99 vci - 4025 - 672 100 lsw - 3955 - 672 no. name x y 101 lsw - 3885 - 672 102 ddvdh - 3815 - 672 103 ddvdh - 3745 - 672 104 ddvdh - 3675 - 672 105 ddvdh - 3605 - 672 106 ddvdh - 3535 - 672 107 ddvdh - 3465 - 672 108 vss - 3395 - 672 109 vss - 3325 - 672 110 vs s - 3255 - 672 111 vss - 3185 - 672 112 vss - 3115 - 672 113 vss - 3045 - 672 114 vss - 2975 - 672 115 vss - 2905 - 672 116 vdd - 2835 - 672 117 vdd - 2765 - 672 118 vdd - 2695 - 672 119 vdd - 2625 - 672 120 vdd - 2555 - 672 121 vdd - 2485 - 672 122 iovcc - 2415 - 672 123 iovcc - 2345 - 672 124 iovcc - 2275 - 672 125 iovcc - 2205 - 672 126 iovcc - 2135 - 672 127 blu_pwm - 2065 - 672 128 blu_en - 1995 - 672 129 test1 - 1925 - 672 130 test2 - 1855 - 672 131 im0 - 1785 - 672 132 im1 - 1715 - 672 133 im2 - 1645 - 672 134 im3 - 1575 - 67 2 135 nreset - 1505 - 672 136 vss_dum - 1435 - 672 137 db<23> - 1365 - 672 138 db<22> - 1295 - 672 139 db<21> - 1225 - 672 140 db<20> - 1155 - 672 141 db<19> - 1085 - 672 142 db<18> - 1015 - 672 143 db<17> - 945 - 672 144 db<16> - 875 - 672 145 db<15> - 805 - 672 14 6 db<14> - 735 - 672 147 db<13> - 665 - 672 148 db<12> - 595 - 672 149 db<11> - 525 - 672 150 db<10> - 455 - 672
LG4572B ver. 1.0. 4 lge confidential 13 no. name x y 151 db<9> - 385 - 672 152 db<8> - 315 - 672 153 db<7> - 245 - 672 154 db<6> - 175 - 672 155 db<5> - 105 - 672 156 db<4> - 35 - 672 157 db<3> 35 - 672 158 db<2> 105 - 672 159 db<1> 175 - 672 160 db<0> 245 - 672 161 rsda 315 - 672 162 nrd_rnw 385 - 672 163 n wr_ e_ sck 455 - 672 164 d n c 525 - 672 165 n cs 595 - 672 166 rscl 665 - 672 167 sdi 735 - 672 168 sdo 805 - 672 169 vsync _te 875 - 672 170 hsync 945 - 672 1 71 de 1015 - 672 172 pclk 1085 - 672 173 v12_sel 1155 - 672 174 dummy 1225 - 672 175 osc1 1295 - 672 176 osc2 1365 - 672 177 osc3 1435 - 672 178 vss_sh1 1505 - 672 179 data 0n 1575 - 672 180 data 0n 1645 - 672 181 data 0n 1715 - 672 182 data 0p 1785 - 672 183 data 0p 1855 - 672 184 data 0p 1925 - 672 185 vss_sh2 1995 - 672 186 data 1n 2065 - 672 187 data 1n 2135 - 672 188 data 1n 2205 - 672 189 data 1p 2275 - 672 190 data 1p 2345 - 672 191 data 1p 2415 - 672 192 vss_sh3 2485 - 672 193 clkn 2555 - 672 194 clkn 2625 - 672 195 clkn 2695 - 672 196 clkp 2765 - 672 197 clkp 2835 - 672 198 clkp 2905 - 672 199 vss_sh4 2975 - 672 200 creg 3045 - 672 201 creg 3115 - 672 202 vcc 3185 - 672 203 vcc 3255 - 672 no. name x y 204 vcc 3325 - 672 205 vcc 3395 - 672 206 vcc 3465 - 672 207 vss 3535 - 67 2 208 vss 3605 - 672 209 vss 3675 - 672 210 vss 3745 - 672 211 vss 3815 - 672 212 vss 3885 - 672 213 vss 3955 - 672 214 vss 4025 - 672 215 vss 4095 - 672 216 vss 4165 - 672 217 vss 4235 - 672 218 vss 4305 - 672 219 vss 4375 - 672 220 vss 4445 - 672 221 vs s 4515 - 672 222 vdd 4585 - 672 223 vdd 4655 - 672 224 vdd 4725 - 672 225 vdd 4795 - 672 226 vdd 4865 - 672 227 vdd 4935 - 672 228 vdd 5005 - 672 229 vdd 5075 - 672 230 vddout 5145 - 672 231 vddout 5215 - 672 232 vddout 5285 - 672 233 vddout 5355 - 672 234 vddout 5425 - 672 235 vreg1out 5495 - 672 236 vgs 5565 - 672 237 ddvdh 5635 - 672 238 ddvdh 5705 - 672 239 ddvdh 5775 - 672 240 ddvdh 5845 - 672 241 ddvdh 5915 - 672 242 ddvdh 5985 - 672 243 ddvdh 6055 - 672 244 ddvdh 6125 - 672 245 c31p 6195 - 672 246 c3 1p 6265 - 672 247 c31p 6335 - 672 248 c31p 6405 - 672 249 c31n 6475 - 672 250 c31n 6545 - 672 251 c31n 6615 - 672 252 c31n 6685 - 672 253 vreg2out 6755 - 672 254 vgs_n 6825 - 672 255 ddvdl 6895 - 672 256 ddvdl 6965 - 672 no. name x y 257 ddvdl 7035 - 672 258 ddvdl 7105 - 672 259 ddvdl 7175 - 672 260 ddvdl 7245 - 672 261 ddvdl 7315 - 672 262 vci 7385 - 672 263 vci 7455 - 672 264 vci 7525 - 672 265 vci 7595 - 672 266 vci 7665 - 672 267 vci 7735 - 672 268 vgh 7805 - 672 269 vgh 7875 - 672 270 vgh 7945 - 672 271 vgh 8015 - 6 72 272 vcom 8085 - 672 273 vcom 8155 - 672 274 vcom 8225 - 672 275 vcom 8295 - 672 276 lvgl 8365 - 672 277 lvgl 8435 - 672 278 lvgl 8505 - 672 279 lvgl 8575 - 672 280 dum_gout 8645 - 672 281 dummy 8715 - 672 282 vcomr 8785 - 672 283 dum_von 8855 - 672 284 vcom 8925 - 672 285 vcom 8995 - 672 286 vcom 9065 - 672 287 dummy 9135 - 672 288 gout_test2 9205 - 672 289 lvgl 9275 - 672 290 lvgl 9345 - 672 291 lvgl 9415 - 672 292 vbias 9485 - 672 293 vgl 9555 - 672 294 vgl 9625 - 672 295 vgl 9695 - 672 296 vgl 9765 - 672 297 gvst2_r 9835 - 672 298 gvst1_r 9905 - 672 299 gclk1_r 9975 - 672 300 gclk1_r 10045 - 672 301 gclk2_r 10115 - 672 302 gclk2_r 10185 - 672 303 gclk3_r 10255 - 672 304 gclk3_r 10325 - 672 305 gclk4_r 10395 - 672 306 gclk4_r 10465 - 672 307 gpwr2_r 10 535 - 672 308 gpwr1_r 10605 - 672 309 bw_r 10675 - 672
LG4572B ver. 1.0. 4 lge confidential 14 no. name x y 310 fw_r 10745 - 672 311 dummy 10815 - 672 312 dummy 10885 - 672 dummy 10950 500 dummy 10935 613 313 s1 10920 500 314 s2 10905 613 315 s3 10890 500 316 s4 10875 613 317 s5 10860 500 318 s6 108 45 613 319 s7 10830 500 320 s8 10815 613 321 s9 10800 500 322 s10 10785 613 323 s11 10770 500 324 s12 10755 613 325 s13 10740 500 326 s14 10725 613 327 s15 10710 500 328 s16 10695 613 329 s17 10680 500 330 s18 10665 613 331 s19 10650 500 332 s20 10635 613 333 s21 10620 500 334 s22 10605 613 335 s23 10590 500 336 s24 10575 613 337 s25 10560 500 338 s26 10545 613 339 s27 10530 500 340 s28 10515 613 341 s29 10500 500 342 s30 10485 613 343 s31 10470 500 344 s32 10455 613 345 s33 10440 500 346 s34 10425 613 347 s35 10410 500 348 s36 10395 613 349 s37 10380 500 350 s38 10365 613 351 s39 10350 500 352 s40 10335 613 353 s41 10320 500 354 s42 10305 613 355 s43 10290 500 356 s44 10275 613 357 s45 10260 500 358 s46 10245 613 359 s47 10230 500 360 s48 10215 613 no. name x y 361 s49 10200 500 362 s50 10185 613 363 s51 10170 500 364 s52 10155 613 365 s53 10140 500 366 s54 10125 613 367 s55 10110 500 368 s56 10095 613 369 s57 10080 500 370 s58 10065 613 371 s59 10050 500 372 s60 1003 5 613 373 s61 10020 500 374 s62 10005 613 375 s63 9990 500 376 s64 9975 613 377 s65 9960 500 378 s66 9945 613 379 s67 9930 500 380 s68 9915 613 381 s69 9900 500 382 s70 9885 613 383 s71 9870 500 384 s72 9855 613 385 s73 9840 500 386 s74 9825 613 387 s75 9810 500 388 s76 9795 613 389 s77 9780 500 390 s78 9765 613 391 s79 9750 500 392 s80 9735 613 393 s81 9720 500 394 s82 9705 613 395 s83 9690 500 396 s84 9675 613 397 s85 9660 500 398 s86 9645 613 399 s87 9630 500 400 s88 9615 613 401 s89 9600 500 402 s90 9585 613 403 s91 9570 500 404 s92 9555 613 405 s93 9540 500 406 s94 9525 613 407 s95 9510 500 408 s96 9495 613 409 s97 9480 500 410 s98 9465 613 411 s99 9450 500 412 s100 9435 613 413 s101 9420 500 no. name x y 414 s102 9405 613 415 s103 9390 500 416 s104 9375 613 417 s105 9360 500 418 s106 9345 613 419 s107 9330 500 420 s108 9315 613 421 s109 9300 500 422 s110 9285 613 423 s111 9270 500 424 s112 9255 613 425 s113 9240 500 426 s114 9225 613 427 s115 9210 500 428 s116 9195 613 429 s117 9180 500 430 s118 9165 613 431 s119 9150 500 432 s120 9135 613 433 s121 9120 500 434 s122 9105 613 435 s123 9090 500 436 s124 9075 613 437 s125 9060 500 438 s126 9045 613 439 s127 9030 500 440 s128 9015 613 441 s129 9000 500 442 s130 8985 613 443 s131 8970 500 444 s132 8955 613 445 s133 8940 500 446 s134 8925 613 447 s135 8910 500 448 s136 8895 613 449 s137 8880 500 450 s138 8865 613 451 s139 8850 500 452 s140 8835 613 453 s141 8820 500 454 s142 8805 613 455 s143 8790 500 456 s144 8775 613 457 s145 8760 500 458 s146 8745 613 459 s147 8730 500 460 s148 8715 613 461 s149 8700 500 462 s150 8685 613 463 s151 8670 500 464 s152 8655 613 465 s153 8640 500 466 s154 8625 613
LG4572B ver. 1.0. 4 lge confidential 15 no. name x y 467 s155 8610 500 468 s156 8595 613 469 s157 8580 500 470 s158 8565 613 471 s159 8550 500 472 s160 8535 613 473 s161 8520 500 474 s162 8505 613 475 s163 8490 500 476 s164 8475 613 477 s165 8460 500 478 s166 8445 613 479 s167 8430 500 480 s168 8415 613 481 s169 8400 500 482 s17 0 8385 613 483 s171 8370 500 484 s172 8355 613 485 s173 8340 500 486 s174 8325 613 487 s175 8310 500 488 s176 8295 613 489 s177 8280 500 490 s178 8265 613 491 s179 8250 500 492 s180 8235 613 493 s181 8220 500 494 s182 8205 613 495 s183 8190 50 0 496 s184 8175 613 497 s185 8160 500 498 s186 8145 613 499 s187 8130 500 500 s188 8115 613 501 s189 8100 500 502 s190 8085 613 503 s191 8070 500 504 s192 8055 613 505 s193 8040 500 506 s194 8025 613 507 s195 8010 500 508 s196 7995 613 509 s1 97 7980 500 510 s198 7965 613 511 s199 7950 500 512 s200 7935 613 513 s201 7920 500 514 s202 7905 613 515 s203 7890 500 516 s204 7875 613 517 s205 7860 500 518 s206 7845 613 519 s207 7830 500 no. name x y 520 s208 7815 613 521 s209 7800 500 522 s210 7785 6 13 523 s211 7770 500 524 s212 7755 613 525 s213 7740 500 526 s214 7725 613 527 s215 7710 500 528 s216 7695 613 529 s217 7680 500 530 s218 7665 613 531 s219 7650 500 532 s220 7635 613 533 s221 7620 500 534 s222 7605 613 535 s223 7590 500 536 s 224 7575 613 537 s225 7560 500 538 s226 7545 613 539 s227 7530 500 540 s228 7515 613 541 s229 7500 500 542 s230 7485 613 543 s231 7470 500 544 s232 7455 613 545 s233 7440 500 546 s234 7425 613 547 s235 7410 500 548 s236 7395 613 549 s237 7380 500 550 s238 7365 613 551 s239 7350 500 552 s240 7335 613 553 s241 7320 500 554 s242 7305 613 555 s243 7290 500 556 s244 7275 613 557 s245 7260 500 558 s246 7245 613 559 s247 7230 500 560 s248 7215 613 561 s249 7200 500 562 s250 7185 613 563 s251 7170 500 564 s252 7155 613 565 s253 7140 500 566 s254 7125 613 567 s255 7110 500 568 s256 7095 613 569 s257 7080 500 570 s258 7065 613 571 s259 7050 500 572 s260 7035 613 no. name x y 573 s261 7020 500 574 s262 7005 613 575 s263 6990 500 576 s264 6975 613 577 s265 6960 500 578 s266 6945 613 579 s267 6930 500 580 s268 6915 613 581 s269 6900 500 582 s270 6885 613 583 s271 6870 500 584 s272 6855 613 585 s273 6840 500 586 s274 6825 613 587 s275 6810 500 588 s276 6795 613 589 s277 6780 500 590 s278 6765 613 591 s279 6750 500 592 s280 6735 613 593 s281 6720 500 594 s282 6705 613 595 s283 6690 500 596 s284 6675 613 597 s285 6660 500 598 s286 6645 613 599 s287 6630 500 600 s288 6615 613 601 s289 6600 500 602 s290 6585 613 603 s291 657 0 500 604 s292 6555 613 605 s293 6540 500 606 s294 6525 613 607 s295 6510 500 608 s296 6495 613 609 s297 6480 500 610 s298 6465 613 611 s299 6450 500 612 s300 6435 613 613 s301 6420 500 614 s302 6405 613 615 s303 6390 500 616 s304 6375 613 61 7 s305 6360 500 618 s306 6345 613 619 s307 6330 500 620 s308 6315 613 621 s309 6300 500 622 s310 6285 613 623 s311 6270 500 624 s312 6255 613 625 s313 6240 500
LG4572B ver. 1.0. 4 lge confidential 16 no. name x y 626 s314 6225 613 627 s315 6210 500 628 s316 6195 613 629 s317 6180 500 630 s318 61 65 613 631 s319 6150 500 632 s320 6135 613 633 s321 6120 500 634 s322 6105 613 635 s323 6090 500 636 s324 6075 613 637 s325 6060 500 638 s326 6045 613 639 s327 6030 500 640 s328 6015 613 641 s329 6000 500 642 s330 5985 613 643 s331 5970 500 6 44 s332 5955 613 645 s333 5940 500 646 s334 5925 613 647 s335 5910 500 648 s336 5895 613 649 s337 5880 500 650 s338 5865 613 651 s339 5850 500 652 s340 5835 613 653 s341 5820 500 654 s342 5805 613 655 s343 5790 500 656 s344 5775 613 657 s345 5 760 500 658 s346 5745 613 659 s347 5730 500 660 s348 5715 613 661 s349 5700 500 662 s350 5685 613 663 s351 5670 500 664 s352 5655 613 665 s353 5640 500 666 s354 5625 613 667 s355 5610 500 668 s356 5595 613 669 s357 5580 500 670 s358 5565 613 671 s359 5550 500 672 s360 5535 613 673 s361 5520 500 674 s362 5505 613 675 s363 5490 500 676 s364 5475 613 677 s365 5460 500 678 s366 5445 613 no. name x y 679 s367 5430 500 680 s368 5415 613 681 s369 5400 500 682 s370 5385 613 683 s371 5370 500 684 s372 5355 613 685 s373 5340 500 686 s374 5325 613 687 s375 5310 500 688 s376 5295 613 689 s377 5280 500 690 s378 5265 613 691 s379 5250 500 692 s380 5235 613 693 s381 5220 500 694 s382 5205 613 695 s383 5190 500 696 s384 5175 613 697 s385 5160 500 698 s386 5145 613 699 s387 5130 500 700 s388 5115 613 701 s389 5100 500 702 s390 5085 613 703 s391 5070 500 704 s392 5055 613 705 s393 5040 500 706 s394 5025 613 707 s395 5010 500 708 s396 4995 613 709 s397 4980 500 710 s398 4965 613 711 s399 4950 500 712 s400 4935 613 713 s401 4920 500 714 s402 4905 613 715 s403 4890 500 716 s404 4875 613 717 s405 4860 500 718 s406 4845 613 719 s407 4830 500 720 s408 4815 613 721 s409 4800 500 722 s410 4785 613 723 s411 4770 500 724 s412 4755 613 725 s413 4740 500 726 s414 4725 613 727 s415 4710 500 728 s416 4695 613 729 s417 4680 500 730 s418 4665 613 731 s419 4650 500 no. name x y 732 s420 4635 613 733 s421 4620 500 734 s422 4605 613 735 s423 4590 500 736 s424 4575 613 737 s425 4560 500 738 s42 6 4545 613 739 s427 4530 500 740 s428 4515 613 741 s429 4500 500 742 s430 4485 613 743 s431 4470 500 744 s432 4455 613 745 s433 4440 500 746 s434 4425 613 747 s435 4410 500 748 s436 4395 613 749 s437 4380 500 750 s438 4365 613 751 s439 4350 50 0 752 s440 4335 613 753 s441 4320 500 754 s442 4305 613 755 s443 4290 500 756 s444 4275 613 757 s445 4260 500 758 s446 4245 613 759 s447 4230 500 760 s448 4215 613 761 s449 4200 500 762 s450 4185 613 763 s451 4170 500 764 s452 4155 613 765 s4 53 4140 500 766 s454 4125 613 767 s455 4110 500 768 s456 4095 613 769 s457 4080 500 770 s458 4065 613 771 s459 4050 500 772 s460 4035 613 773 s461 4020 500 774 s462 4005 613 775 s463 3990 500 776 s464 3975 613 777 s465 3960 500 778 s466 3945 6 13 779 s467 3930 500 780 s468 3915 613 781 s469 3900 500 782 s470 3885 613 783 s471 3870 500 784 s472 3855 613
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LG4572B ver. 1.0. 4 lge confidential 22 no. name x y 1580 s1264 - 8280 500 1581 s1265 - 8295 613 1582 s1266 - 8310 500 1583 s1267 - 8325 613 1584 s1268 - 8340 500 1585 s1269 - 8355 613 1586 s1270 - 8370 500 1587 s1271 - 8385 613 1588 s1272 - 8400 500 1589 s1273 - 8415 613 1590 s1274 - 8430 500 1591 s1275 - 8445 613 1592 s1276 - 8460 500 1593 s1277 - 8475 613 1594 s1278 - 8490 500 1595 s1279 - 8505 613 1596 s1280 - 8520 500 1597 s1281 - 8535 613 1598 s12 82 - 8550 500 1599 s1283 - 8565 613 1600 s1284 - 8580 500 1601 s1285 - 8595 613 1602 s1286 - 8610 500 1603 s1287 - 8625 613 1604 s1288 - 8640 500 1605 s1289 - 8655 613 1606 s1290 - 8670 500 1607 s1291 - 8685 613 1608 s1292 - 8700 500 1609 s1293 - 8715 613 1610 s1294 - 8730 500 1611 s1295 - 8745 613 1612 s1296 - 8760 500 1613 s1297 - 8775 613 1614 s1298 - 8790 500 1615 s1299 - 8805 613 1616 s1300 - 8820 500 1617 s1301 - 8835 613 1618 s1302 - 8850 500 1619 s1303 - 8865 613 1620 s1304 - 8880 500 1621 s1305 - 88 95 613 1622 s1306 - 8910 500 1623 s1307 - 8925 613 1624 s1308 - 8940 500 1625 s1309 - 8955 613 1626 s1310 - 8970 500 1627 s1311 - 8985 613 1628 s1312 - 9000 500 1629 s1313 - 9015 613 1630 s1314 - 9030 500 1631 s1315 - 9045 613 1632 s1316 - 9060 500 no. name x y 1633 s 1317 - 9075 613 1634 s1318 - 9090 500 1635 s1319 - 9105 613 1636 s1320 - 9120 500 1637 s1321 - 9135 613 1638 s1322 - 9150 500 1639 s1323 - 9165 613 1640 s1324 - 9180 500 1641 s1325 - 9195 613 1642 s1326 - 9210 500 1643 s1327 - 9225 613 1644 s1328 - 9240 500 1645 s1329 - 9255 613 1646 s1330 - 9270 500 1647 s1331 - 9285 613 1648 s1332 - 9300 500 1649 s1333 - 9315 613 1650 s1334 - 9330 500 1651 s1335 - 9345 613 1652 s1336 - 9360 500 1653 s1337 - 9375 613 1654 s1338 - 9390 500 1655 s1339 - 9405 613 1656 s1340 - 9420 500 1657 s1341 - 9435 613 1658 s1342 - 9450 500 1659 s1343 - 9465 613 1660 s1344 - 9480 500 1661 s1345 - 9495 613 1662 s1346 - 9510 500 1663 s1347 - 9525 613 1664 s1348 - 9540 500 1665 s1349 - 9555 613 1666 s1350 - 9570 500 1667 s1351 - 9585 613 1668 s1352 - 9600 500 1669 s1353 - 9615 613 1670 s1354 - 9630 500 1671 s1355 - 9645 613 1672 s1356 - 9660 500 1673 s1357 - 9675 613 1674 s1358 - 9690 500 1675 s1359 - 9705 613 1676 s1360 - 9720 500 1677 s1361 - 9735 613 1678 s1362 - 9750 500 1679 s1363 - 9765 6 13 1680 s1364 - 9780 500 1681 s1365 - 9795 613 1682 s1366 - 9810 500 1683 s1367 - 9825 613 1684 s1368 - 9840 500 1685 s1369 - 9855 613 no. name x y 1686 s1370 - 9870 500 1687 s1371 - 9885 613 1688 s1372 - 9900 500 1689 s1373 - 9915 613 1690 s1374 - 9930 500 1691 s1375 - 9945 613 1692 s1376 - 9960 500 1693 s1377 - 9975 613 1694 s1378 - 9990 500 1695 s1379 - 10005 613 1696 s1380 - 10020 500 1697 s1381 - 10035 613 1698 s1382 - 10050 500 1699 s1383 - 10065 613 1700 s1384 - 10080 500 1701 s1385 - 10095 613 1702 s1386 - 10110 500 1703 s1387 - 10125 613 1704 s1388 - 10140 500 1705 s1389 - 10155 613 1706 s1390 - 10170 500 1707 s1391 - 10185 613 1708 s1392 - 10200 500 1709 s1393 - 10215 613 1710 s1394 - 10230 500 1711 s1395 - 10245 613 1712 s1396 - 10260 500 1713 s1397 - 10275 61 3 1714 s1398 - 10290 500 1715 s1399 - 10305 613 1716 s1400 - 10320 500 1717 s1401 - 10335 613 1718 s1402 - 10350 500 1719 s1403 - 10365 613 1720 s1404 - 10380 500 1721 s1405 - 10395 613 1722 s1406 - 10410 500 1723 s1407 - 10425 613 1724 s1408 - 10440 500 1725 s1409 - 10455 613 1726 s1410 - 10470 500 1727 s1411 - 10485 613 1728 s1412 - 10500 500 1729 s1413 - 10515 613 1730 s1414 - 10530 500 1731 s1415 - 10545 613 1732 s1416 - 10560 500 1733 s1417 - 10575 613 1734 s1418 - 10590 500 1735 s1419 - 10605 613 173 6 s1420 - 10620 500 1737 s1421 - 10635 613 1738 s1422 - 10650 500
LG4572B ver. 1.0. 4 lge confidential 23 no. name x y 1739 s1423 - 10665 613 1740 s1424 - 10680 500 1741 s1425 - 10695 613 1742 s1426 - 10710 500 1743 s1427 - 10725 613 1744 s1428 - 10740 500 1745 s1429 - 10755 613 1746 s1430 - 10770 500 1747 s 1431 - 10785 613 1748 s1432 - 10800 500 1749 s1433 - 10815 613 1750 s1434 - 10830 500 1751 s1435 - 10845 613 1752 s1436 - 10860 500 1753 s1437 - 10875 613 1754 s1438 - 10890 500 1755 s1439 - 10905 613 1756 s1440 - 10920 500 dummy - 10935 613 dummy - 10950 500 alignment mark x y ? (1 - a) - 11,060 600 ? (1 - b) 11,060 600
LG4572B ver. 1.0. 4 lge confidential 24 4.4 bump arrangement staggered (no. 313 C 1756) i/o pins in - line (no. 1 - 312) 1 5 1 5 1 5 1 5 a r e a = 1 4 7 0 u m 2 9 8 1 5 9 8 1 1 3 5 0 a r e a = 4 0 0 0 u m 2 7 0 8 0
LG4572B ver. 1.0. 4 lge confidential 25 5 functional description 5.1 mipi dbi type - a the lg 457 2b supports mipi dbi type - a (m68 interface). 5.1.1 write cycle sequence during a write cycle the host processor writes commands or data to the lg 4572b via the interface. type a interface utilize s ncs , dnc , nrd_rnw and nwr_e_sck signals as well as all eight (d b [7 :0]), nine (d b [8:0]) , sixteen (d b [15:0]) , eighteen (db[17:0]), or twenty - four (db[23:0]) information signals. dnc is driven low while a command is present on the interface and pulled high when data is on the interface. the following figure shows the writ e cycle for the type a interface . figure 2 . dbi type a interface write cycle note: 1. nwr_e_sck is an unsynchronized signal; it can be stopped 2. ncs is asserted(taken low) for the same duration a s the information signals the following figure shows the example of write cycle sequence for the type a interface. n w r _ e _ s c k d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] t h e h o s t a s s e r t s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s w h e n t h e r e i s r i s i n g e d g e o f n w r _ e _ s c k t h e l g 4 5 7 2 r e a d s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s w h e n t h e r e i s f a l l i n g e d g e o f n w r _ e _ s c k t h e h o s t n e g a t e s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s
LG4572B ver. 1.0. 4 lge confidential 26 figure 3 . dbi type a interface write cycle sequence example 5.1.2 read cycle sequence dur ing a read cycle the host processor reads data from the lg 4572b via the interface. type a interface utilize s ncs , d n c, r n w and nwr_e_sck signals as well as all eight (d b [7:0]), nine (d b [8:0]) , sixteen (d b [15:0]) , eighteen (db[17:0]), or twenty - four [db[23 :0] ] information signals. dnc is driven low during the entire read cycle. figure 4 . dbi type a interface read cycle sequence note: 1. nwr_e_sck is an unsynchronized signal; it can be stopped. 2. nc s is asserted(taken low) for the same duration as the information signals. the following figure shows the example of write cycle sequence for the type a interface. n c s n r e s e t d n c n r d _ r n w n w r _ e _ s c k d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] i n t e r f a c e h o s t d i s p l a y h i - z c o m m a n d c o m m a n d d a t a d a t a f i x e d c l o c k e d n w r _ e _ s c k m o d e w r i t e s e q u e n c e n w r _ e _ s c k d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] t h e l g 4 5 7 2 a s s e r t s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s w h e n t h e r e i s r i s i n g e d g e o f n w r _ e _ s c k t h e h o s t r e a d s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s w h e n t h e r e i s f a l l i n g e d g e o f n w r _ e _ s c k t h e l g 4 5 7 2 n e g a t e s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s
LG4572B ver. 1.0. 4 lge confidential 27 figure 5 . dbi type a interface read cycle sequence example 5.2 mipi dbi type - b the lg 4572b supports mipi dbi type - b (i80 interface). 5.2.1 write cycle sequence during a write cycle, data and/or command are written to the lg 4572b via the interface between the lg 4572b and the host processor. each s tep of write cycle sequence (nwr_e_sck high, nwr_e_sck low, nwr_e_sck high) comprises three control signals (d n c, nrd_rnw , nwr_e_sck) and 8 - , 9 - , 16 - , 18 - , or 24 bit data. the d n c bit indicates signal that is used to select command or data sent on the da ta bus. when d n c=1, data on the above data bus is image data or command parameter. when d nc = 0, data is command. setting nrd_rnw and nwr_e_sck to low simultaneously is prohibited. see the figure below for the write cycle sequence. the followin g figure shows the write cycle for the type b interface . n c s n r e s e t d n c n r d _ r n w n w r _ e _ s c k d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] i n t e r f a c e h o s t d i s p l a y h i - z c o m m a n d c o m m a n d d a t a ( i n v a l i d ) d a t a ( v a l i d ) d a t a ( i n v a l i d ) h i - z h i - z d a t a ( v a l i d ) f i x e d c l o c k e d n w r _ e _ s c k m o d e r e a d s e q u e n c e
LG4572B ver. 1.0. 4 lge confidential 28 figure 6 . dbi type b interface write cycle sequence note: 1. nwr_e_sck is an unsynchronized signal; it can be stopped. the following figure shows an example of the write cycle for the type b interface . figure 7 . dbi type b interface write cycle example 5.2.2 read cycle sequence during a read cycle, data and/or commands are read from the lg 4 572b via the interface between the lg 4572b and the host processor. the data ( db[23:0], db[17:0], [15:0], [8:0] or [7:0]) are n w r _ e _ s c k d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] t h e h o s t a s s e r t s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s w h e n t h e r e i s f a l l i n g e d g e o f n w r _ e _ s c k t h e l g 4 5 7 2 r e a d s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s w h e n t h e r e i s r i s i n g e d g e o f n w r _ e _ s c k t h e h o s t n e g a t e s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s n c s n r e s e t d n c n w r _ e _ s c k n r d _ r n w d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] i n t e r f a c e h o s t d i s p l a y h i - z c o m m a n d c o m m a n d d a t a d a t a w r i t e s e q u e n c e d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ]
LG4572B ver. 1.0. 4 lge confidential 29 transmitted from the lg 4572b to the host processor on the falling edge of nrd_rnw. the host processor reads the data on the ris ing edge of nrd_rnw. setting nrd_rnw and nwr_e_sck to low simultaneously is prohibited. see below for the read cycle sequence. figure 8 . dbi type b interface read cycle sequence. note: 1. : nrd_ rnw is not a synchronous signal (can be halted). the following figure shows an example of the read cycle for the type b interface . figure 9 . dbi type b interface read cycle sequence example n r d _ r n w d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] t h e l g 4 5 7 2 a s s e r t s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s w h e n t h e r e i s f a l l i n g e d g e o f n r d _ r n w t h e h o s t r e a d s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s w h e n t h e r e i s r i s i n g e d g e o f n r d _ r n w t h e l g 4 5 7 2 n e g a t e s d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] l i n e s n c s n r e s e t d n c n w r _ e _ s c k n r d _ r n w d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] i n t e r f a c e h o s t d i s p l a y r e a d s e q u e n c e d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] d b [ ( 2 3 / 1 7 / 1 5 / 8 / 7 ) : 0 ] h i - z c o m m a n d c o m m a n d d a t a ( i n v a l i d ) d a t a ( v a l i d ) d a t a ( i n v a l i d ) h i - z h i - z d a t a ( v a l i d )
LG4572B ver. 1.0. 4 lge confidential 30 5.2.3 interf ace color coding for dbi type a and b the lg 4572b supports 8 - bit/9 - bit/16 - bit/18 - bit/24 - bit color codings for dbi type a and b. the following figures are for them. 8 - bit interface figure 10 . 16 - bit s/pixel(r 5 - bit, g 6 - bit, b 5 - bit), 65,536 colors d / c x w r x o f t y p e b e o f t y p e a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r 1 , b i t 4 r 1 , b i t 3 r 1 , b i t 2 r 1 , b i t 1 r 1 , b i t 0 g 1 , b i t 5 g 1 , b i t 4 p i x e l n g 1 , b i t 2 g 1 , b i t 1 g 1 , b i t 0 b 1 , b i t 4 b 1 , b i t 3 b 1 , b i t 2 b 1 , b i t 1 b 1 , b i t 0 r 2 , b i t 4 r 2 , b i t 3 r 2 , b i t 2 r 2 , b i t 1 r 2 , b i t 0 g 2 , b i t 5 g 2 , b i t 4 g 2 , b i t 3 g 1 , b i t 2 g 2 , b i t 1 g 2 , b i t 0 b 2 , b i t 4 b 2 , b i t 3 b 2 , b i t 2 b 2 , b i t 1 b 2 , b i t 0 b i t 6 b i t 7 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 g 1 , b i t 3 p i x e l n + 1
LG4572B ver. 1.0. 4 lge confidential 31 figure 11 . 18 - bits/pixel(r 6 - bit, g 6 - bit, b 6 - bit), 262,144 colors figure 12 . 24 - bits/pixel(r 8 - bit, g 8 - bit, b 8 - bit), 16,777,216 colors d / c x w r x o f t y p e b e o f t y p e a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r 1 , b i t 4 r 1 , b i t 3 r 1 , b i t 2 r 1 , b i t 1 r 1 , b i t 0 g 1 , b i t 5 g 1 , b i t 4 p i x e l n g 1 , b i t 2 g 1 , b i t 1 g 1 , b i t 0 b 1 , b i t 4 b 1 , b i t 3 b 1 , b i t 2 b 1 , b i t 1 b 1 , b i t 0 r 2 , b i t 4 r 2 , b i t 3 r 2 , b i t 2 r 2 , b i t 1 r 2 , b i t 0 b i t 6 b i t 7 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 g 1 , b i t 3 p i x e l n + 1 r 1 , b i t 5 b 1 , b i t 5 r 2 , b i t 5 d / c x w r x o f t y p e b e o f t y p e a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r 1 , b i t 4 r 1 , b i t 3 r 1 , b i t 2 r 1 , b i t 1 r 1 , b i t 0 g 1 , b i t 5 g 1 , b i t 4 p i x e l n g 1 , b i t 2 g 1 , b i t 1 g 1 , b i t 0 b 1 , b i t 4 b 1 , b i t 3 b 1 , b i t 2 b 1 , b i t 1 b 1 , b i t 0 r 2 , b i t 4 r 2 , b i t 3 r 2 , b i t 2 r 2 , b i t 1 r 2 , b i t 0 b i t 6 b i t 7 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 g 1 , b i t 3 p i x e l n + 1 r 1 , b i t 5 b 1 , b i t 5 r 2 , b i t 5 r 1 , b i t 6 g 1 , b i t 7 g 1 , b i t 6 b 1 , b i t 6 r 2 , b i t 6 r 1 , b i t 7 b 1 , b i t 7 r 2 , b i t 7
LG4572B ver. 1.0. 4 lge confidential 32 9 - bit interface figure 13 . 18 - bits/pixel(r 6 - bit, g 6 - bit, b 6 - bit), 262,144 colors d / c x w r x o f t y p e b e o f t y p e a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r 1 , b i t 4 r 1 , b i t 3 r 1 , b i t 2 r 1 , b i t 1 r 1 , b i t 0 g 1 , b i t 5 g 1 , b i t 4 p i x e l n g 1 , b i t 1 g 1 , b i t 0 b 1 , b i t 5 b 1 , b i t 4 b 1 , b i t 3 b 1 , b i t 2 b 1 , b i t 1 b 1 , b i t 0 r 2 , b i t 4 r 2 , b i t 3 r 2 , b i t 2 r 2 , b i t 1 r 2 , b i t 0 g 2 , b i t 5 g 2 , b i t 4 g 2 , b i t 3 g 1 , b i t 1 g 2 , b i t 0 b 2 , b i t 5 b 2 , b i t 4 b 2 , b i t 3 b 2 , b i t 2 b 2 , b i t 1 b 2 , b i t 0 b i t 6 b i t 7 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 g 1 , b i t 3 p i x e l n + 1 r 1 , b i t 5 g 1 , b i t 2 r 2 , b i t 5 g 1 , b i t 2 b i t 8 d 8
LG4572B ver. 1.0. 4 lge confidential 33 16 - bit interface figure 14 . 16 - bits/pixel(r 5 - bit, g 6 - bit, b 5 - bit), 65,536 colors d / c x w r x o f t y p e b e o f t y p e a d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 r 1 , b i t 4 r 1 , b i t 3 r 1 , b i t 2 r 1 , b i t 1 g 1 , b i t 5 g 1 , b i t 4 p i x e l n g 1 , b i t 0 r 2 , b i t 3 r 2 , b i t 2 r 2 , b i t 1 r 2 , b i t 0 g 2 , b i t 5 g 2 , b i t 4 g 2 , b i t 3 b i t 1 5 b i t 1 4 b i t 1 3 b i t 1 2 b i t 1 1 b i t 1 0 b i t 9 g 1 , b i t 3 p i x e l n + 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 g 1 , b i t 1 b 1 , b i t 4 b 1 , b i t 3 b 1 , b i t 2 b 1 , b i t 1 b 1 , b i t 0 g 2 , b i t 0 g 2 , b i t 1 g 2 , b i t 2 b i t 6 b i t 7 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 g 1 , b i t 2 b i t 8 d 8 r 1 , b i t 0 r 2 , b i t 4 b 2 , b i t 0 b 2 , b i t 4 b 2 , b i t 3 b 2 , b i t 2 b 2 , b i t 1 r 3 , b i t 3 r 3 , b i t 2 r 3 , b i t 1 r 3 , b i t 0 g 3 , b i t 5 g 3 , b i t 4 g 3 , b i t 3 g 3 , b i t 0 g 3 , b i t 1 g 3 , b i t 2 r 3 , b i t 4 b 3 , b i t 0 b 3 , b i t 4 b 3 , b i t 3 b 3 , b i t 2 b 3 , b i t 1 p i x e l n + 2
LG4572B ver. 1.0. 4 lge confidential 34 figure 15 . 18 - bits/pixel(r 6 - bit, g 6 - bit, b 6 - bit), 262,144 colors d / c x w r x o f t y p e b e o f t y p e a d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 r 1 , b i t 4 r 1 , b i t 3 r 1 , b i t 2 r 1 , b i t 1 g 1 , b i t 5 g 1 , b i t 4 p i x e l n g 1 , b i t 0 r 2 , b i t 3 r 2 , b i t 2 r 2 , b i t 1 r 2 , b i t 0 g 2 , b i t 5 g 2 , b i t 4 g 2 , b i t 3 b i t 1 5 b i t 1 4 b i t 1 3 b i t 1 2 b i t 1 1 b i t 1 0 b i t 9 g 1 , b i t 3 p i x e l n + 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 g 1 , b i t 1 b 1 , b i t 4 b 1 , b i t 3 b 1 , b i t 2 b 1 , b i t 1 b 1 , b i t 0 g 2 , b i t 0 g 2 , b i t 1 g 2 , b i t 2 b i t 6 b i t 7 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 g 1 , b i t 2 b i t 8 d 8 r 1 , b i t 0 r 2 , b i t 4 b 2 , b i t 0 b 2 , b i t 5 b 2 , b i t 3 b 2 , b i t 2 b 2 , b i t 1 r 1 , b i t 5 b 1 , b i t 5 r 2 , b i t 5 b 2 , b i t 4
LG4572B ver. 1.0. 4 lge confidential 35 figure 16 . 24 - bits/pixel(r 8 - bit, g 8 - bit, b 8 - bit), 16,777,216 colors d / c x w r x o f t y p e b e o f t y p e a d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 r 1 , b i t 4 r 1 , b i t 3 r 1 , b i t 2 r 1 , b i t 1 g 1 , b i t 5 g 1 , b i t 4 p i x e l n g 1 , b i t 0 r 2 , b i t 3 r 2 , b i t 2 r 2 , b i t 1 r 2 , b i t 0 g 2 , b i t 5 g 2 , b i t 4 g 2 , b i t 3 b i t 1 5 b i t 1 4 b i t 1 3 b i t 1 2 b i t 1 1 b i t 1 0 b i t 9 g 1 , b i t 3 p i x e l n + 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 g 1 , b i t 1 b 1 , b i t 4 b 1 , b i t 3 b 1 , b i t 2 b 1 , b i t 1 b 1 , b i t 0 g 2 , b i t 0 g 2 , b i t 1 g 2 , b i t 2 b i t 6 b i t 7 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 g 1 , b i t 2 b i t 8 d 8 r 1 , b i t 0 r 2 , b i t 4 b 2 , b i t 0 b 2 , b i t 5 b 2 , b i t 3 b 2 , b i t 2 b 2 , b i t 1 r 1 , b i t 7 b 1 , b i t 5 r 2 , b i t 5 b 2 , b i t 4 r 1 , b i t 5 r 1 , b i t 6 g 1 , b i t 7 g 1 , b i t 6 r 2 , b i t 7 r 2 , b i t 6 b 2 , b i t 7 b 2 , b i t 6 g 2 , b i t 7 g 2 , b i t 6 b 1 , b i t 6 b 1 , b i t 7
LG4572B ver. 1.0. 4 lge confidential 36 18 - bit interface figure 17 . 18 - bits/pixel(r 6 - bit, g 6 - bit, b 6 - bit), 262,144 colors d / c x w r x o f t y p e b e o f t y p e a d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 g 1 , b i t 5 g 1 , b i t 4 p i x e l n g 1 , b i t 0 r 2 , b i t 3 r 2 , b i t 2 r 2 , b i t 1 r 2 , b i t 0 g 2 , b i t 5 g 2 , b i t 4 g 2 , b i t 3 b i t 1 5 b i t 1 4 b i t 1 3 b i t 1 2 b i t 1 1 b i t 1 0 b i t 9 g 1 , b i t 3 p i x e l n + 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 g 1 , b i t 1 b 1 , b i t 1 b 1 , b i t 0 g 2 , b i t 0 g 2 , b i t 1 g 2 , b i t 2 b i t 6 b i t 7 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 g 1 , b i t 2 b i t 8 d 8 r 2 , b i t 4 b 2 , b i t 0 b 2 , b i t 5 b 2 , b i t 3 b 2 , b i t 2 b 2 , b i t 1 r 2 , b i t 5 b 2 , b i t 4 d 1 7 d 1 6 b i t 1 7 b i t 1 6 r 1 , b i t 1 r 1 , b i t 0 d 2 3 d 2 2 d 2 1 d 2 0 d 1 9 d 1 8 r 1 , b i t 4 r 1 , b i t 3 r 1 , b i t 2 b i t 2 3 b i t 2 2 b i t 2 1 b i t 2 0 b i t 1 9 b i t 1 8 b 1 , b i t 4 b 1 , b i t 3 b 1 , b i t 2 b 1 , b i t 5 r 1 , b i t 5 p i x e l n + 2 r 3 , b i t 3 r 3 , b i t 2 r 3 , b i t 1 r 3 , b i t 0 g 3 , b i t 5 g 3 , b i t 4 g 3 , b i t 3 g 3 , b i t 0 g 3 , b i t 1 g 3 , b i t 2 r 3 , b i t 4 b 3 , b i t 0 b 3 , b i t 5 b 3 , b i t 3 b 3 , b i t 2 b 3 , b i t 1 r 3 , b i t 5 b 3 , b i t 4
LG4572B ver. 1.0. 4 lge confidential 37 24 - bit interface figure 18 . 24 - bits/pixel(r 8 - bit, g 8 - bit, b 8 - bit), 16,777,216 colors d / c x w r x o f t y p e b e o f t y p e a d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 g 1 , b i t 5 g 1 , b i t 4 p i x e l n g 1 , b i t 0 r 2 , b i t 3 r 2 , b i t 2 r 2 , b i t 1 r 2 , b i t 0 g 2 , b i t 5 g 2 , b i t 4 g 2 , b i t 3 b i t 1 5 b i t 1 4 b i t 1 3 b i t 1 2 b i t 1 1 b i t 1 0 b i t 9 g 1 , b i t 3 p i x e l n + 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 g 1 , b i t 1 b 1 , b i t 1 b 1 , b i t 0 g 2 , b i t 0 g 2 , b i t 1 g 2 , b i t 2 b i t 6 b i t 7 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 g 1 , b i t 2 b i t 8 d 8 r 2 , b i t 4 b 2 , b i t 0 b 2 , b i t 5 b 2 , b i t 3 b 2 , b i t 2 b 2 , b i t 1 r 2 , b i t 5 b 2 , b i t 4 g 1 , b i t 7 g 1 , b i t 6 r 2 , b i t 7 r 2 , b i t 6 b 2 , b i t 7 b 2 , b i t 6 g 2 , b i t 7 g 2 , b i t 6 d 1 7 d 1 6 b i t 1 7 b i t 1 6 r 1 , b i t 1 r 1 , b i t 0 d 2 3 d 2 2 d 2 1 d 2 0 d 1 9 d 1 8 r 1 , b i t 4 r 1 , b i t 3 r 1 , b i t 2 b i t 2 3 b i t 2 2 b i t 2 1 b i t 2 0 b i t 1 9 b i t 1 8 b 1 , b i t 4 b 1 , b i t 3 b 1 , b i t 2 r 1 , b i t 7 b 1 , b i t 5 r 1 , b i t 5 r 1 , b i t 6 b 1 , b i t 6 b 1 , b i t 7 p i x e l n + 2 r 3 , b i t 3 r 3 , b i t 2 r 3 , b i t 1 r 3 , b i t 0 g 3 , b i t 5 g 3 , b i t 4 g 3 , b i t 3 g 3 , b i t 0 g 3 , b i t 1 g 3 , b i t 2 r 3 , b i t 4 b 3 , b i t 0 b 3 , b i t 5 b 3 , b i t 3 b 3 , b i t 2 b 3 , b i t 1 r 3 , b i t 5 b 3 , b i t 4 r 3 , b i t 7 r 3 , b i t 6 b 3 , b i t 7 b 3 , b i t 6 g 3 , b i t 7 g 3 , b i t 6
LG4572B ver. 1.0. 4 lge confidential 38 5.2.4 interface color coding for gram data write there are different possible gram data writing way s in the lg 4572b according to each 8 - bit/9 - bit/16 - bit/18 - bit/24 - bit interfaces . the following figures are for them. 8 - bit interface ? 2 - transfers ( 65,536 colors 16 - bits/pixel ) ? 3 - transfers ( 262,144 colors 1 8 - bits/pixel ) ? 3 - transfers ( 16,777,216 colors 24 - bits/pixel ) 1 s t 2 n d d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 r 4 r 3 r 2 r 1 r 0 g 5 g 4 g 3 g 2 g 1 g 0 b 4 b 3 b 2 b 1 b 0 g r a m 2 3 g r a m 2 2 g r a m 2 1 g r a m 2 0 g r a m 1 9 g r a m 1 8 g r a m 1 7 g r a m 1 6 g r a m 1 5 g r a m 1 4 g r a m 1 3 g r a m 1 2 g r a m 1 1 g r a m 1 0 g r a m 9 g r a m 8 g r a m 7 g r a m 6 g r a m 5 g r a m 4 g r a m 3 g r a m 2 g r a m 1 g r a m 0 0 0 0 0 0 0 r 4 r 3 r 5 r 7 r 6 r 7 g 5 g 4 g 3 g 2 g 7 g 6 b 4 b 3 b 7 b 5 b 6 b 7 1 s t 2 n d d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 r 4 r 3 r 2 r 1 r 0 r 5 b 4 b 3 b 2 b 1 b 0 g r a m 2 3 g r a m 2 2 g r a m 2 1 g r a m 2 0 g r a m 1 9 g r a m 1 8 g r a m 1 7 g r a m 1 6 g r a m 1 5 g r a m 1 4 g r a m 1 3 g r a m 1 2 g r a m 1 1 g r a m 1 0 g r a m 9 g r a m 8 g r a m 7 g r a m 6 g r a m 5 g r a m 4 g r a m 3 g r a m 2 g r a m 1 g r a m 0 0 0 0 0 0 0 3 r d x x d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 g 5 g 4 g 3 g 2 g 1 g 0 x x x x b 5 r 4 r 3 r 2 r 5 r 7 r 6 g 5 g 4 g 3 g 2 g 7 g 6 b 4 b 3 b 2 b 5 b 6 b 7 1 s t 2 n d d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 r 4 r 3 r 2 r 1 r 0 r 5 b 4 b 3 b 2 b 1 b 0 g r a m 2 3 g r a m 2 2 g r a m 2 1 g r a m 2 0 g r a m 1 9 g r a m 1 8 g r a m 1 7 g r a m 1 6 g r a m 1 5 g r a m 1 4 g r a m 1 3 g r a m 1 2 g r a m 1 1 g r a m 1 0 g r a m 9 g r a m 8 g r a m 7 g r a m 6 g r a m 5 g r a m 4 g r a m 3 g r a m 2 g r a m 1 g r a m 0 3 r d r 7 r 6 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 g 5 g 4 g 3 g 2 g 1 g 0 b 5 g 7 g 6 b 6 b 7 r 4 r 3 r 2 r 1 r 0 r 5 b 4 b 3 b 2 b 1 b 0 r 7 r 6 g 5 g 4 g 3 g 2 g 1 g 0 b 5 g 7 g 6 b 6 b 7
LG4572B ver. 1.0. 4 lge confidential 39 9 - bit interface ? 2 - transfers ( 262,144 colors 1 8 - bits/pixel ) 16 - bit interface ? 1 - transfer ( 65,536 colors 16 - b its/pixel ) ? 1.5 - transfers ( 262,144 colors 1 8 - bits/pixel ) ? 1.5 - transfers ( 16,777,216 colors 24 - bits/pixel ) 1 s t 2 n d d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 r 4 r 3 r 2 r 1 r 0 g 5 g 4 g 3 g 2 g 1 g 0 b 4 b 3 b 2 b 1 b 0 g r a m 2 3 g r a m 2 2 g r a m 2 1 g r a m 2 0 g r a m 1 9 g r a m 1 8 g r a m 1 7 g r a m 1 6 g r a m 1 5 g r a m 1 4 g r a m 1 3 g r a m 1 2 g r a m 1 1 g r a m 1 0 g r a m 9 g r a m 8 g r a m 7 g r a m 6 g r a m 5 g r a m 4 g r a m 3 g r a m 2 g r a m 1 g r a m 0 0 0 0 0 0 0 r 4 r 3 r 5 r 7 r 6 r 2 g 5 g 4 g 3 g 2 g 7 g 6 b 4 b 3 b 2 b 5 b 6 b 7 d b 8 r 5 d b 8 b 5 1 s t d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 r 4 r 3 r 2 r 1 r 0 g r a m 2 3 g r a m 2 2 g r a m 2 1 g r a m 2 0 g r a m 1 9 g r a m 1 8 g r a m 1 7 g r a m 1 6 g r a m 1 5 g r a m 1 4 g r a m 1 3 g r a m 1 2 g r a m 1 1 g r a m 1 0 g r a m 9 g r a m 8 g r a m 7 g r a m 6 g r a m 5 g r a m 4 g r a m 3 g r a m 2 g r a m 1 g r a m 0 0 0 0 0 0 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 g 5 g 4 g 3 g 2 g 1 g 0 r 4 r 3 r 7 r 5 r 7 r 6 g 5 g 4 g 3 g 2 g 7 g 6 b 4 b 3 b 7 b 5 b 6 b 7 b 4 b 3 b 2 b 1 b 0 1 s t d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 9 d b 8 r 4 r 3 r 2 r 1 r 0 g r a m 2 3 g r a m 2 2 g r a m 2 1 g r a m 2 0 g r a m 1 9 g r a m 1 8 g r a m 1 7 g r a m 1 6 g r a m 1 5 g r a m 1 4 g r a m 1 3 g r a m 1 2 g r a m 1 1 g r a m 1 0 g r a m 9 g r a m 8 g r a m 7 g r a m 6 g r a m 5 g r a m 4 g r a m 3 g r a m 2 g r a m 1 g r a m 0 0 0 0 0 0 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 g 5 g 4 g 3 g 2 g 1 g 0 r 4 r 3 r 2 r 5 r 7 r 6 g 5 g 4 g 3 g 2 g 7 g 6 b 4 b 3 b 2 b 5 b 6 b 7 b 4 b 3 b 2 b 1 b 0 d b 1 0 r 5 x x x x 2 n d d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 d b 1 0 b 5 x x r 4 r 3 r 2 r 1 r 0 r 5 x x 1 s t d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 9 d b 8 r 4 r 3 r 2 r 1 r 0 g r a m 2 3 g r a m 2 2 g r a m 2 1 g r a m 2 0 g r a m 1 9 g r a m 1 8 g r a m 1 7 g r a m 1 6 g r a m 1 5 g r a m 1 4 g r a m 1 3 g r a m 1 2 g r a m 1 1 g r a m 1 0 g r a m 9 g r a m 8 g r a m 7 g r a m 6 g r a m 5 g r a m 4 g r a m 3 g r a m 2 g r a m 1 g r a m 0 g 1 g 0 b 1 b 0 r 1 r 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 g 5 g 4 g 3 g 2 g 1 g 0 r 4 r 3 r 2 r 5 r 7 r 6 g 5 g 4 g 3 g 2 g 7 g 6 b 4 b 3 b 2 b 5 b 6 b 7 b 4 b 3 b 2 b 1 b 0 d b 1 0 r 5 2 n d d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 d b 1 0 b 5 r 6 r 7 g 7 g 6 b 6 b 7 r 4 r 3 r 2 r 1 r 0 r 5 r 6 r 7
LG4572B ver. 1.0. 4 lge confidential 40 18 - bit interface ? 1 - transfer ( 262,144 colors 1 8 - bit s/pixel ) 24 - bit interface ? 1 - transfer ( 16,777,216 colors 24 - bits/pixel ) 1 s t d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 9 d b 8 r 4 r 3 r 2 r 1 r 0 g r a m 2 3 g r a m 2 2 g r a m 2 1 g r a m 2 0 g r a m 1 9 g r a m 1 8 g r a m 1 7 g r a m 1 6 g r a m 1 5 g r a m 1 4 g r a m 1 3 g r a m 1 2 g r a m 1 1 g r a m 1 0 g r a m 9 g r a m 8 g r a m 7 g r a m 6 g r a m 5 g r a m 4 g r a m 3 g r a m 2 g r a m 1 g r a m 0 0 0 0 0 0 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 g 5 g 4 g 3 g 2 g 1 g 0 r 4 r 3 r 2 r 5 r 7 r 6 g 5 g 4 g 3 g 2 g 7 g 6 b 4 b 3 b 2 b 5 b 6 b 7 b 4 b 3 b 2 b 1 b 0 d b 1 0 r 5 b 5 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b 1 7 d b 1 6 d b 1 8 x x x x x x r 6 r 7 g 7 g 6 b 6 b 7 1 s t d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 9 d b 8 r 4 r 3 r 2 r 1 r 0 g r a m 2 3 g r a m 2 2 g r a m 2 1 g r a m 2 0 g r a m 1 9 g r a m 1 8 g r a m 1 7 g r a m 1 6 g r a m 1 5 g r a m 1 4 g r a m 1 3 g r a m 1 2 g r a m 1 1 g r a m 1 0 g r a m 9 g r a m 8 g r a m 7 g r a m 6 g r a m 5 g r a m 4 g r a m 3 g r a m 2 g r a m 1 g r a m 0 g 1 g 0 b 1 b 0 r 1 r 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 g 5 g 4 g 3 g 2 g 1 g 0 r 4 r 3 r 2 r 5 r 7 r 6 g 5 g 4 g 3 g 2 g 7 g 6 b 4 b 3 b 2 b 5 b 6 b 7 b 4 b 3 b 2 b 1 b 0 d b 1 0 r 5 b 5 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b 1 7 d b 1 6 d b 1 8
LG4572B ver. 1.0. 4 lge confidential 41 5.3 mipi dbi type c the lg 4572b supports mipi dbi type c (4 - wire 9 - bit serial interface). 5.3.1 write cycle seque nce during a write cycle the host processor sends a single bit of data to the display module via the interface. the t ype c interface utilizes ncs , sc k and sd i signals. sck is driven from high to low then pulled back to high during the write cycle. the host processor provides information during the write cycle while the display module reads the host processor information on the rising edge of sc k . the following figure shows the write cycle for the type c interface. figure 19 . dbi type c interface write cycle note: sc k is an unsynchronized signal; it can be stopped. during the write sequence the host processor writes one or more bytes of information to the display module via the interface. the write sequen ce is initiated when ncs is driven from high to low and ends when ncs is pulled high. each byte is nine write cycles in length. the type c interface write sequences is described in figure 20 . figure 20 . dbi type c interface write sequence 5.3.2 read cycle sequence during a read cycle the host processor reads a single bit of data from the display module via the interface. the t ype c interface utilizes ncs , sc k and sdo signals. sc k is driven from high to low then pulled back to high during the read cycle. the display module provides information during the read cycle while the host processor reads the display module information on the rising edge of sc k . t h e h o s t a s s e r t s s d i p i n w h e n t h e r e i s a f a l l i n g e d g e o f s c k . t h e d i s p l a y r e a d s s d i p i n w h e n t h e r e i s a r i s i n g e d g e o f s c k . s c k s d i s c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d / n c d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 s d i n c s c o m m a n d t h e n e x t c o m m a n d o r t h e f o l l o w i n g d a t a s d o d o n t c a r e
LG4572B ver. 1.0. 4 lge confidential 42 figure 21 shows the read cycle for the type c interface. figure 21 . dbi type c interface read cycle note: sc k is an unsynchronized signal; it can be stopped. during the read se quence the host processor reads one or more bytes of information from the display module via the interface. the read sequence is initiated when ncs is driven from high to low and ends when ncs is pulled high. each byte is nine read cycles in length. the ty pe c interface read sequence is shown in figure 22 . figure 22 . dbi type c interface read sequence 5.3.3 break and pause of sequences the host processor can break a r ead or write sequence by pulling the ncs signal high during a command or data byte. the display module shall reset its interface so it will be ready to receive the same byte when ncs is again driven low. the host processor can pause a read or write sequenc e by pulling the ncs signal high between command or data bytes. the display module shall wait for the host processor to drive ncs low before continuing the read or write sequence at the point where the sequence was paused. 5.3.4 data transfer break as shown in the figure below, in the transmission of parameter for command from the host processor to the lg 4572b , the command parameters sent to the lg 4572b before the break occurs are stored in the register of the lg 4572b when the following two conditions are met . one is that a break occurs before the last parameter of the command is sent to the lg 4572b . the t h e d i s p l a y a s s e r t s s d o p i n w h e n t h e r e i s a f a l l i n g e d g e o f s c k . t h e h o s t r e a d s s d o p i n w h e n t h e r e i s a r i s i n g e d g e o f s c k . s c k s d o s c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 s d i n c s r e a d c o m m a n d r e a d d a t a s d o x x x x x x x x x d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x
LG4572B ver. 1.0. 4 lge confidential 43 other is that the host processor transmits the parameter(s) of a new command, not the parameters of the interrupted command, when the break occurs. howe ver, those parameters sent after the break is disregarded, and the data in the register is not overwritten. note : a break is occurred, for example, by other command input. figure 23 . d iagram of d ata transfer break sequence c o m m a n d 1 p a r a m e t e r 1 p a r a m e t e r 2 p a r a m e t e r 3 w h i l e s e n d i n g p a r a m e t e r c o m m a n d s , i f a b r e a k o c c u r s b e f o r e s e n d i n g t h e l a s t p a r a m e t e r , t h o s e p a r a m e t e r s s e n t a f t e r t h e b r e a k a r e a r e g a r d e d . c o m m a n d 1 p a r a m e t e r 1 s t o r e d i n t h e r e g i s t e r p a r a m e t e r 2 t h e d a t a i n t h e r e g i s t e r i s n o t o v e r w r i t t e n p a r a m e t e r 3 t h e d a t a i n t h e r e g i s t e r i s n o t o v e r w r i t t e n c o m m a n d 2 p a r a m e t e r f o r c o m m a n d 2 b r e a k d i s r e g a r d e d a b r e a k i n d a t a t r a n s f e r o c c u r s d u e t o i n t e r v e n t i o n b y o t h e r c o m m a n d s , e t c .
LG4572B ver. 1.0. 4 lge confidential 44 5.4 mipi dpi - 2 5.4.1 interface signals table 1 . interface signals for dpi symbol name i/o description vsync vertical sync i vertical synchronization timing signal hsync horizontal sync i horizontal synchronizatio n timing signal de data enable i data enable signal (assertion indicates valid pixels) pclk pixel clock i pixel clock for capturing pixels at display interface db[15:0], db[17:0] or db[23:0] pixel data i pixel data in 16 - bit, 18 - bit, or 24 - bit format 5.4.2 i nterface color coding table 2 specifies the mapping of data bits, as components of primary pixel color values r, g, and b, to signal lines at the interface. note: lg 4572b supports configuration 1 and 3 for 16 - bit pi xels, configuration 1 and 2 for 18 - bit pixels and 24 - bit pixels. 3ah and b1h are the related registers. table 2 . interface color coding signal line 16 - bit 18 - bit 24 - bit configuration 1 configuration 2 configuration 3 configuratio n 1 configuration 2 d23 (not used) (not used) (not used) (not used) (not used) r7 d22 (not used) (not used) (not used) (not used) (not used) r6 d21 (not used) (not used) r4 (not used) r5 r5 d20 (not used) r4 r3 (not used) r4 r4 d19 (not used) r3 r2 ( not used) r3 r3 d18 (not used) r2 r1 (not used) r2 r2 d17 (not used) r1 r0 r5 r1 r1 d16 (not used) r0 (not used) r4 r0 r0 d15 r4 (not used) (not used) r3 (not used) g7 d14 r3 (not used) (not used) r2 (not used) g6 d13 r2 g5 g5 r1 g5 g5 d12 r1 g4 g4 r0 g4 g4 d11 r0 g3 g3 g5 g3 g3 d10 g5 g2 g2 g4 g2 g2 d9 g4 g1 g1 g3 g1 g1 d8 g3 g0 g0 g2 g0 g0 d7 g2 (not used) (not used) g1 (not used) b7 d6 g1 (not used) (not used) g0 (not used) b6 d5 g0 (not used) b4 b5 b5 b5 d4 b4 b4 b3 b4 b4 b4 d3 b3 b3 b2 b3 b3 b3 d2 b2 b2 b1 b2 b2 b2 d1 b1 b1 b0 b1 b1 b1 d0 b0 b0 (not used) b0 b0 b0 there are three mappings for 16 - bit pixels to data signals, two mappings for 18 - bit pixels to data signals, and one mapping for 24 - bit pixels to data signals.
LG4572B ver. 1.0. 4 lge confidential 45 notes: pixel values are specified as triplets for primary color components r, g, and b: r = red, g = green, b = blue. r0 is the lsb for the red component, g0 is lsb for the green component, etc. for 16 - bit pixels, r primary color msb is r4, r primary color lsb is r0; g primary color msb is g5, g primary color lsb is g0; b primary color msb is b4 and b primary color lsb is b0. for 18 - bit pixels, r primary color msb is r5, r primary color lsb is r0; g primary color msb is g5, g primary color lsb is g0; b primary color m sb is b5 and b primary color lsb is b0. for 24 - bit pixels, r primary color msb is r7, r primary color lsb is r0; g primary color msb is g7, g primary color lsb is g0; b primary color msb is b7 and b primary color lsb is b0. 5.4.3 interface timing parameter in n ormal operation, systems based on dpi architecture rely on the host processor to continuously provide complete frames of image data at a sufficient frame rate to avoid flicker or other visible artifacts. the displayed image, or frame , is comprised of a re ctangular array of pixels. the frame is transmitted from the host processor to a display module as a sequence of pixels, with each horizontal line of the image data s ent as a group of consecutive pixels. vsync indicates the beginning of each frame of the displayed image. hsync signals the beginning of each horizontal line of pixels. each pixel value (16 - , 18 - , or 24 - bit data) is transferred from the host processor to the display module during one pixel period. the rising edge of pclk is used by the displ ay module to capture pixel data. since pclk runs continuously, control signal de is required to indicate when valid pixel data is being transmitted on the pixel data signals. figure 35 defines timing parameters for dpi operation. figure 24 . dpi parameter
LG4572B ver. 1.0. 4 lge confidential 46 table 3 . interface signals for dpi parameters symbols min. step max. unit horizontal synchronization hsync 1 1 - pclk horizontal back porch hbp 1 1 - pclk horizontal address hadr 240 (320, 360) - 480 pclk horizontal front porch hfp 1 1 - pclk vertical synchronization vsync 1 1 - line vertical back porch vbp 1 1 - line vertical address vadr 176 4 864 line vertical front porch vfp 1 1 - line note s: 1. vertical period (one frame) shall be equa l to the sum of vsync + vbp + vadr + vfp. 2. horizontal period (one line) shall be equal to the sum of hsync + hbp + hadr + hfp. 3. control signals pclk and hsync shall be transmitted as specified at all times while valid pixels are transferred between the host processor and the display module.
LG4572B ver. 1.0. 4 lge confidential 47 5.5 spi ( serial peripheral interface) the serial interface is selected by setting the im[2:0] = 110x for register access while mipi dpi/ dsi is used for pixel data streaming lg 4572b . the data is transferred via chip se lect line (ncs), serial transfer clock line (sc k ), serial data input line (sdi), and serial data output line (sdo). in serial interface operation, the im[0] pin functions as the id pin, and the db[23:0] pins, not used in this mode, must be fixed at either iovcc or gnd level. the lg 4572b recognizes the start of data transfer on the falling edge of ncs input and starts transferring the start byte. it recognizes the end of data transfer on the rising edge of ncs input. the lg 4572b is selected when the 6 - bit ch ip address in the start byte transferred from the transmission unit and the 6 - bit device identification code assigned to the lg 4572b are compared and both 6 - bit data match, and then the lg 4572b starts taking in data. the least significant bit of the device identification code is set with the id pin. send "01110 to the five upper bits of the device identification code. two different chip addresses must be assigned to the lg 4572b because the seventh bit of the start byte is assigned to the register select bi t (rs). when rs = 0, an index register write operation is executed. when rs = 1, either an instruction write operation or a ram read/write operation is executed. the eighth bit of the start byte is to select either read or write operation (r/w bit). the lg 4572b receives data when the r/w = 0, and transfers data when the r/w = 1. after receiving the start byte, the lg 4572b starts transferring or receiving data in units of bytes. the lg 4572b executes data transfer from the msb. table 4 . start b yte f ormat transferred bits 1 2 3 4 5 6 7 8 start byte format device id code rs r/w 0 1 1 1 0 im[0] note: id bit is selected by setting the im0/id pin. table 5 . rs r/w function 0 0 set an index register 0 1 read a status 1 0 write an instruction or ram data 1 1 read an instruction or ram data 5.5.1 write cycle sequence figure 25 . spi interface s c k 1 1 1 0 i d r s r / w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 s d i n c s d a t a t r a n s f e r s d o d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0
LG4572B ver. 1.0. 4 lge confidential 48 the following figures demonstrate the serial reading operation in the fah register for example. figure 26 . example for serial data reading figure 27 . example for serial data reading C continued n c s 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 s c k s d i s d o d o n t c a r e 0 1 1 1 0 0 0 0 1 1 1 1 1 0 1 0 d o n t c a r e c s 1 2 3 4 5 6 7 8 s c k s d i s d o d o n t c a r e d u m m y d a t a 0 1 1 1 0 0 1 1 d a t a 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 . . .
LG4572B ver. 1.0. 4 lge confidential 49 5.6 mipi dsi dsi s pecifies the interface between a host processor and a peripheral such as a display module. it builds on existing mipi alliance specifications by adopting pixel formats and command set specified in dpi - 2, dbi - 2 and dcs standards. figure 28 shows a simplified dsi interface. from a conceptual viewpoint, a dsi - compliant interface performs the same functions as interfaces based on dbi - 2 and dpi - 2 standards or similar parallel display interfaces. it sends pixels or comman ds to the peripheral, and can read back status or pixel information from the peripheral. the main difference is that dsi serializes all pixel data, commands, and events that, in traditional or legacy interfaces, are normally conveyed to and from the periph eral on a parallel data bus with additional control signals. from a system or software point of view, the serialization and deserialization operations should be transparent. the most visible, and unavoidable, consequence of transformation to serial data an d back to parallel is increased latency for transactions that require a response from the peripheral. for example, reading a pixel from the frame buffer on a display module has a higher latency using dsi than dbi. another fundamental difference is the host processor?s inability during a read transaction to throttle the rate, or size, of returned data. figure 28 . mipi dsi transmitter and receiver interface h o s t d e v i c e , e . g . a n a p p l i c a t i o n p r o c e s s o r o r b a s e b a n d p r o c e s s o r c o n t a i n i n g h s t r a n s m i t t e r , l p t r a n s m i t t e r , l p r e c e i v e r l g 4 5 7 2 w i t h h s r e c e i v e r , l p r e c e i v e r , a n d l p t r a n s m i t t e r ( f o r b i d i r e c t i o n a l o n l y ) d a t a 1 p d a t a 1 n c l k p c l k n d a t a 0 p d a t a 0 n n u m b e r o f d a t a l a n e s c a n b e 1 , 2 , 3 , o r 4 d a t a 1 + d a t a 1 - c l o c k + c l o c k - d a t a 0 + d a t a 0 - h i g h s p e e d d a t a l i n k s ( l a n e 0 m a y b e b i d i r e c t i o n a l i n l p m o d e )
LG4572B ver. 1.0. 4 lge confidential 50 5.6.1 dsi layer definitions figure 29 . dsi layers a conceptual view of dsi organizes the interface into several functional layers. a description of the layers follows and is also shown in figure 29 . phy layer: the phy layer specifies transmission medium (electrical conductors), the input/output circuitry and the clocking mechanism that captures ones and zeroes from the serial bit stream. this part of the specification documents the characteristics of the transm ission medium, electrical parameters for signaling and the timing relationshi p between clock and data lanes. the mechanism for signaling start of transmission (sot) and end of transmission (eot) is specified, as well as other out of band information that can be conveyed between transmitting and receiving phys. bit - level and byte - level synchronization mechanisms are included as part of the phy. note that the electrical basis for dsi (slvs) has two distinct modes of operation, each with its own set of elect rical parameters. the phy layer is described in mipi all iance specification for d - phy . lane management layer: dsi is lane - scalable for increased performance. the number of data signals may be 1, 2, 3, or 4 depending on the bandwidth requirements of the app lication. the transmitter side of the interface distributes the outgoing data stream to one or more lanes (distributor function). on the receiving end, the interface collects bytes from the lanes and merges them together into a recombined data stream tha t restores the original stream sequence (merger function). protocol layer: at the lowest level, dsi protocol specifies the sequence and value of bits and bytes traversing the interface. it specifies how bytes are organized into defined groups called pack ets. the protocol defines required headers for each packet, and how header information is generated and a p p l i c a t i o n l o w l e v e l p r o t o c o l l a n e m a n a g e m e n t p h y l a y e r p i x e l t o b y t e p a c k i n g f o r m a t s c o m m a n d g e n e r a t i o n / i n t e r p r e t a t i o n p a c k e t b a s e d p r o t o c o l e c c a n d c h e c k s u m g e n e r a t i o n a n d t e s t i n g l a n e d i s t r i b u t i o n a n d m e r g i n g s t a r t o f p a c k e t / e n d o f p a c k e t s e r i a l i z e r / d e s e r i a l i z e r c l o c k m a n a g e m e n t ( d d r ) e l e c t r i c a l l a y e r ( s l v s ) a p p l i c a t i o n l o w l e v e l p r o t o c o l l a n e m a n a g e m e n t p h y l a y e r a p p l i c a t i o n p r o c e s s o r p e r i p h e r a l l a n e 0 C h i g h s p e e d d a t a ( o p t i o n a l l y b i d i r e c t i o n a l i n l p m o d e ) d a t a c o n t r o l d a t a c o n t r o l d a t a c o n t r o l d a t a c o n t r o l d a t a c o n t r o l d a t a c o n t r o l d a t a c o n t r o l d a t a ( n + 1 ) x 8 b i t s 8 b i t s 8 b i t s ( n + 1 ) x 8 b i t s 8 b i t s 8 b i t s c o n t r o l h i g h s p e e d u n i d i r e c t i o n a l c l o c k l a n e n C h i g h s p e e d u n i d i r e c t i o n a l d a t a
LG4572B ver. 1.0. 4 lge confidential 51 interpreted. the transmitting side of the interface appends header and error - checking information to data being transmitted. on the receiving side, the header is stripped off and interpreted by corresponding logic in the receiver. error - checking information may be used to test the integrity of incoming data. dsi protocol also documents how packets may be tagged for interleaving multiple command or data st reams to separate destinations using a sin gle dsi. application layer: this layer describes higher - level encoding and interpretation of data contained in the data stream. depending on the display subsystem architecture, it may consist of pixels having a pre scribed format, or of commands that are interpreted by the display controller inside a display module. the dsi specification describes the mapping of pixel values, commands and command parameters to bytes in the packet assembly. see mipi alliance standard for display command set (dcs) . 5.6.2 command and video modes dsi - compliant peripherals support either of two basic modes of operation: command mode and video mode. which mode is used depends on the architecture and capabilities of the peripheral. the mode defini tions reflect the primary intended use of dsi for display interconnect, but are not intended to restrict dsi from operating in other applications. typically, a peripheral is capable of command mode operation or video mode operation. some video mode display modules also include a simplified form of command mode operation in which the display module may refresh its screen from a reduced - size, or partial, frame buffer, and the interface (dsi) to the host processor may be shut down to reduce power consumption. command mode command mode refers to operation in which transactions primarily take the form of sending commands and data to a peripheral, such as a display module, that incorporates a display controller. the display controller may include local registers a nd a frame buffer. systems using command mode write to, and read from, the registers and frame buffer memory. the host processor indirectly controls activity at the peripheral by sending commands, parameters and data to the display controller. the host pro cessor can also read display module status information or the contents of the frame memory. command mode operation requires a bidirectional interface. video mode video mode refers to operation in which transfers from the host processor to the peripheral ta ke the form of a real - time pixel stream. in normal operation, the display module relies on the host processor to provide image data at sufficient bandwidth to avoid flicker or other visible artifacts in the displayed image. video information should only be transmitted using high speed mode. some video mode architectures may include a simple timing controller and partial frame buffer, used to maintain a partial - screen or lower - resolution image in standby or low power mode. this permits the interface to be sh ut down to reduce power consumption. to reduce complexity and cost, systems that only operate in video mode may use a unidirectional data path. virtual channel capability while this specification only addresses the connection of a host processor to a singl e peripheral, dsi incorporates a virtual channel capability for communication between a host processor and multiple, physical display modules. display modules are completely independent, may operate simultaneously, and may be of different display architect ure types, limited only by the total bandwidth available over the shared dsi link. the details of connecting multiple peripherals to a single link are beyond the scope of this document. since interface bandwidth is shared between peripherals, there are con straints that limit the physical extent and performance of multiple - peripheral systems.
LG4572B ver. 1.0. 4 lge confidential 52 the dsi protocol permits up to four virtual channels, enabling traffic for multiple peripherals to share a common dsi link. in some high - resolution display designs, mu ltiple physical drivers serve different areas of a common display panel. each driver is integrated with its own display controller that connects to the host processor through dsi. using virtual channels, the display controller directs data to the individua l drivers, eliminating the need for multiple interfaces or complex multiplexing schemes . 5.6.3 dsi physical layer (d - phy) the lg 4572b supports mipi d - phy specification of version 0.90.00 C 8 october 2007 . the d - phy provides a synchronous connection between maste r and slave. a practical phy configuration consists of a clock signal and one or more data signals. the clock signal is unidirectional, originating at the master and terminating at the slave. the data signals can either be unidirectional or bi - directional depending on the selected options. for half - duplex operation, the reverse direction bandwidth is one - fourth of the forward direction bandwidth. token passing is used to control the communication direction of the link. the link includes a high - speed signali ng mode for fast - data traffic and a low - power signaling mode for control purposes. optionally, a low - power escape mode can be used for low speed asynchronous data communication. high speed data communication appears in bursts with an arbitrary number of pa yload data bytes. the phy uses two wires per data lane plus two wires for the clock lane. this gives four wires for the minimum phy configuration. in high - speed mode each lane is terminated on both sides and driven by a low - swing, differential signal. in low - power mode all wires are operated single - ended and non - terminated. for emi reasons, the drivers for this mode shall be slew - rate controlled and current limited. the maximum bit rate in high - speed mode of the lg 4572b is 330 mbps per lane. 8 for a fixed c lock frequency, the available data capacity of a phy configuration can be increased by using more data lanes. effective data throughput can be reduced by employing burst mode communication. the maximum data rate in low - power mode is 10mbps. 5.6.4 interconnect th e following figure 30 and figure 31 show the pad connection to the tft - lcd panel which is proposed to be driven by lg 4572b . from this, we recommend, for better performance, that the resistance from pads to wires is as small as possible. for the best performance, we recommend the r tab + r olb + r fog resistance values of mipi power block pad are below 5 ohms for each. and the those of communication pad are recommended to below 5 ohms for each to minimize the influence of the impedance matching of high - speed receiver blocks, and to reduce the external resistance load of the low - power transmitter block. 8 the actual maximum achievable bit rate in high - speed mode is determ ined by the performance of transmitter, receiver and interconnect implementations. therefore, the maximum bit rate is not specified in the d - phy specification .
LG4572B ver. 1.0. 4 lge confidential 53 figure 30 . pad connecti on from mipi block (inside chip) to the external power capacitor of cb1 and clock/data wires. figure 31 . consideration of the resistance. r cog + r olb + r fog < 10ohm. assuming the other resistances of fpc patterns or c onnectors are negligibly small. 5.6.5 d - phy signal voltage levels & speed there are two signaling voltage levels for d - phy. as shown in the following figure, on e is 1.2v voltage level signaling for a low - speed data transmission(lp:low power, und er 10mbps) and the other is 200mv peak - to - peak voltage swing level for a high - speed data transmission(hs:high speed, up to 330 mbps ). generally, the lp signaling is used for a command transmission and a read operation(from peripheral to host), and the hs s ignaling is used for an image data transmission. m i p i d - p h y b l o c k ( i n s i d e c h i p ) c b c r e g c r e g d a t a 1 n d a t a 1 p c l k n c l k p v s s _ s h 2 v s s _ s h 3 v s s _ s h 4 s h i e l d i n g l i n e f r o m c o u p l i n g n o i s e s h i e l d i n g l i n e f r o m c o u p l i n g n o i s e s h i e l d i n g l i n e f r o m c o u p l i n g n o i s e d a t a 0 n d a t a 0 p v s s _ s h 1 s h i e l d i n g l i n e f r o m c o u p l i n g n o i s e m i p i d - p h y b l o c k ( i n s i d e c h i p ) c r e g c r e g d a t a 1 n d a t a 1 p c l k n c l k p v s s _ s h 2 v s s _ s h 3 v s s _ s h 4 d a t a 0 n d a t a 0 p v s s _ s h 1 g l a s s o l b d - i c f p c r t a b r o l b r c o g
LG4572B ver. 1.0. 4 lge confidential 54 figure 32 . line voltage levels of d - phy 5.6.6 high speed data transmission with d - phy if a host processor want to transmit some data using d - phy in high speed mode, as shown in the fo llowing figure, the host must follow the following sequences. - sot sequence ? dsi data packets ? eot sequence - sot sequence : lp - 11 ? lp - 01 ? lp - 00(t hs - prepare ) ? hs - 0(t hs - zero ) ? sync command ? 00011101 ? (t hs - sync ) - eot sequence : toggles the last data and keeps for a time t hs - trail ? lp - 11 figure 33 . high speed data transmission sequence with d - phy 5.6.7 low power data transmission with d - phy if a host processor want to transmit some data using d - phy low power mode, as show n in the following figure, the host must follows the sequence below. - escape mode entry ? lpdt command ? 11100001 ? ? dsi data packets ? exit escape - escape mode entry : lp - 11 ? lp - 10 ? lp - 00 ? lp - 01 ? lp - 00 - exit escape : lp - 10 ? lp - 11
LG4572B ver. 1.0. 4 lge confidential 55 figure 34 . low power data transmission sequence with d - phy 5.6.8 dsi protocol on the transmitter side of a dsi link, parallel data, signal events, and commands are converted in the protocol layer to packets, following the packet organization docume nted in this section. the protocol layer appends packet - protocol information and headers, and then sends complete bytes through the lane management layer to the phy. packets are serialized by the phy and sent across the serial link. the receiver side of a dsi link performs the converse of the transmitter side, decomposing the packet into parallel data, signal events and commands . general packet structure two packet structures are defined for low - level protocol communication: long packets and short packets. for both packet structures, the data identifier is always the first byte of the packet. long packet format figure 35 shows the structure of the long packet. a long packet shall consist of three elements: a 32 - bit p acket header (ph), an application - specific data payload with a variable number of bytes, and a 16 - bit packet footer (pf). the packet header is further composed of three elements: an 8 - bit data identifier, a 16 - bit word count, and 8 - bit ecc. the packet foot er has one element, a 16 - bit checksum. long packets can be from 6 to 65,541 bytes in length.
LG4572B ver. 1.0. 4 lge confidential 56 figure 35 . long packet structure short packet format fig ure 36 sho ws the structure of the short packet. a short packet shall contain an 8 - bit data id followed by two command or data bytes and an 8 - bit ecc; a packet footer shall not be present. short packets shall be four bytes in length. fig ure 36 . short packet structure data identifier byte the first byte of any packet is the di (data identifier) byte. di[7:6]: these two bits identify the data as directed to one of four virtual channels. 1 6 - b i t c h e c k s u m w o r d c o u n t ( w c ) l p s s o t l p s e o t d a t a i d e c c d a t a 0 d a t a 1 d a t a w c - 1 d a t a w c - 2 3 2 - b i t p a c k e t h e a d e r ( p h ) 1 6 - b i t p a c k e t f o o t e r ( p f ) a p p l i c a t i o n s p e c i f i c p a y l o a d c h e c k s u m ( c s ) d a t a i d e n t i f i e r ( d i ) : c o n t a i n s v i r t u a l c h a n n e l i d e n t i f i e r a n d d a t a t y p e i n f o r m a t i o n d a t a t y p e d e n o t e s t h e f o r m a t a n d c o n t e n t o f a p p l i c a t i o n - s p e c i f i c p a y l o a d d a t a 1 6 - b i t w o r d c o u n t ( w c ) : t h e w o r d c o u n t c o n v e y s h o w m a n y w o r d s ( b y t e s ) a r e i n p a c k e t p a y l o a d t h e r e c e i v e r u s e s w c t o d e t e r m i n e t h e p a c k e t e n d ( a f t e r p a y l o a d + c h e c k s u m ) 8 - b i t e r r o r c o r r e c t i o n c o d e ( e c c ) f o r t h e p a c k e t h e a d e r : 8 - b i t e c c f o r t h e p a c k e t h e a d e r , p r o t e c t s u p t o 8 b y t e s i n h e a d e r e n a b l e s o n e - b i t e r r o r s i n p a c k e t h e a d e r t o b e c o r r e c t e d a n d t w o - b i t e r r o r s t o b e d e t e c t e d p a c k e t d a t a ( p a y l o a d ) : l e n g t h = w c * d a t a w o r d s i z e ( 8 - b i t s ) n o v a l u e r e s t r i c t i o n s o n d a t a w o r d s i n p a y l o a d l p s s o t l p s e o t d a t a i d e c c d a t a 0 d a t a 1 p a c k e t h e a d e r ( p h ) d a t a i d e n t i f i e r ( d i ) : c o n t a i n s t h e v i r t u a l c h a n n e l i n d e n t i f i e r a n d t h e d a t a t y p e i n f o r m a t i o n d a t a t y p e d e n o t e s t h e f o r m a t / c o n t e n t o f t h e a p p l i c a t i o n s p e c i f i c p a y l o a d d a t a u s e d b y t h e a p p l i c a t i o n l a y e r p a c k e t d a t a : l e n g t h i s f i x e d a t t w o b y t e s t h e r e a r e n o v a l u e r e s t r i c t i o n s o n d a t a w o r d s 8 - b i t e r r o r c o r r e c t i o n c o d e ( e c c ) f o r t h e p a c k e t h e a d e r : 8 - b i t e c c f o r t h e p a c k e t h e a d e r a l l o w s o n e - b i t e r r o r s w i t h i n t h e p a c k e t h e a d e r t o b e c o r r e c t e d a n d t w o - b i t e r r o r s t o b e d e t e c t e d
LG4572B ver. 1.0. 4 lge confidential 57 di[5:0]: these six bits spec ify the data type. table 6 . data types for processor - sourced packets data type, hex data type, binary description packet size 01h 00 0001 sync event, v sync start short 11h 01 0001 sync event, v sync end short 21h 10 0001 sync ev ent, h sync start short 31h 11 0001 sync event, h sync end short 08h 00 1000 end of transmission packet (eotp) short 02h 00 0010 color mode (cm) off command short 12h 01 0010 color mode (cm) on command short 22h 10 0010 shut down peripheral command sh ort 32h 11 0010 turn on peripheral command short 03h 00 0011 generic short write, no parameters short 13h 01 0011 generic short write, 1 parameter short 23h 10 0011 generic short write, 2 parameters short 04h 00 0100 generic read, no parameters short 14h 01 0100 generic read, 1 parameter short 24h 10 0100 generic read, 2 parameters short 05h 00 0101 dcs short write, no parameters short 15h 01 0101 dcs short write, 1 parameter short 06h 00 0110 dcs read, no parameters short 37h 11 0111 set maximum return packet size short 09h 00 1001 null packet, no data long 19h 01 1001 blanking packet, no data long 29h 10 1001 generic long write long 39h 11 1001 dcs long write/write_lut command packet long 0eh 00 1110 packed pixel stream, 16 - bit rgb, 5 - 6 - 5 f ormat long 1eh 01 1110 packed pixel stream, 18 - bit rgb, 6 - 6 - 6 format long 2eh 10 1110 loosely packed pixel stream, 18 - bit rgb, 6 - 6 - 6 format long 3eh 11 1110 packed pixel stream, 24 - bit rgb, 8 - 8 - 8 format long x0h and xfh , unspecified xx 0000 xx 1111 do not use all unspecified codes are reserved error correction code the error correction code allows single - bit errors to be corrected and 2 - bit errors to be detected in the packet header. the host processor shall always calculate and transmit an ecc byte. peripherals shall support ecc in both forward - and reverse - direction communicatio ns. video mode packed pixel stream there are several data packet structure for pixel data transmission, 16 - bit (5 - 6 - 5) format, two 18 - bit (6 - 6 - 6) formats, 24 - bit format (8 - 8 - 8) and each data packet structure is shown in the following figures.
LG4572B ver. 1.0. 4 lge confidential 58 figure 37 . packed pixel stream, 16 - bit rgb, 5 - 6 - 5 format d a t a i d e c c w o r d c o u n t d a t a t y p e v i r t u a l c h a n n e l . . . c h e c k s u m . . . 1 b y t e 2 b y t e s 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 2 b y t e s c h e c k s u m p a c k e t h e a d e r v a r i a b l e s i z e p a y l o a d 5 b 5 b 5 b 5 b 6 b 6 b p i x e l 1 p i x e l n p i x e l 1 0 r 0 4 r 4 5 g 0 7 g 2 2 g 5 3 b 0 1 b y t e 1 b y t e 0 g 3 7 b 4 5 b 6 b 5 b . . . 0 0 5 5 6 0 7 1 0 0 1 5 1 5 0 0 7 7 0 0 1 5 1 5 t i m e
LG4572B ver. 1.0. 4 lge confidential 59 figure 38 . packed p ixel stream, 18 - bit rgb, 6 - 6 - 6 format d a t a i d e c c w o r d c o u n t d a t a t y p e v i r t u a l c h a n n e l c h e c k s u m . . . 1 b y t e 2 b y t e s 1 b y t e 1 b y t e 1 b y t e 2 b y t e s p a c k e t f o o t e r p a c k e t h e a d e r v a r i a b l e s i z e p a y l o a d ( f i r s t f o u r p i x e l s p a c k e d i n n i n e b y t e s ) 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e v a r i a b l e s i z e p a y l o a d ( l a s t f o u r p i x e l s p a c k e d i n n i n e b y t e s ) 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e p i x e l 1 p i x e l 2 p i x e l 3 p i x e l 4 p i x e l n - 3 p i x e l n - 2 p i x e l n - 1 p i x e l n 0 r 0 5 r 5 6 g 0 7 g 1 3 g 5 4 b 0 1 b 5 1 b y t e 1 b y t e p i x e l 1 0 g 2 0 b 4 7 b 3 1 b y t e 6 b 6 b 6 b . . . 0 0 0 0 0 0 0 0 1 5 1 5 1 5 1 5 7 7 5 5 6 0 7 1 t i m e t i m e
LG4572B ver. 1.0. 4 lge confidential 60 figure 39 . loosely packed pixel stream, 18 - bit rgb, 6 - 6 - 6 format d a t a i d e c c w o r d c o u n t d a t a t y p e v i r t u a l c h a n n e l c h e c k s u m . . . 1 b y t e 2 b y t e s 1 b y t e 1 b y t e 1 b y t e 2 b y t e s p a c k e t f o o t e r p a c k e t h e a d e r v a r i a b l e s i z e p a y l o a d ( f i r s t t h r e e p i x e l s i n n i n e b y t e s ) 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e v a r i a b l e s i z e p a y l o a d ( l a s t t h r e e p i x e l s p a c k e d i n n i n e b y t e s ) 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 6 b 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e p i x e l 1 p i x e l 2 p i x e l 3 p i x e l n - 2 p i x e l n - 1 p i x e l n 2 r 0 7 r 5 2 g 0 7 g 5 2 b 0 7 b 5 1 b y t e 1 b y t e p i x e l 1 0 1 0 1 0 1 1 b y t e 6 b 6 b 6 b . . . 0 0 0 0 0 0 0 0 1 5 1 5 1 5 1 5 7 7 5 5 6 0 7 1 t i m e t i m e
LG4572B ver. 1.0. 4 lge confidential 61 figure 40 . packed pixel stream, 24 - bit rgb, 8 - 8 - 8 format video mode interface timing dsi supports several formats, or packet sequences, for video mode data transmission. the peripheral?s timing requirements dictate which format is appropriate. in the following sections, burst mode refers to time - co mpression of the rgb pixel (active video) portion of the transmission. in addition, these terms are used throughout the following sections: ? non - burst mode with sync pulses C enables the peripheral to accurately reconstruct original video timing, including sync pulse widths. ? non - burst mode with sync events C similar to above, but accurate reconstruction of sync pulse widths is not required, so a single sync event is substituted. ? burst mode C rgb pixel packets are time - compressed, leaving more time during a s can line for lp mode (saving power) or for multiplexing other transmissions onto the dsi link. d a t a i d e c c w o r d c o u n t d a t a t y p e v i r t u a l c h a n n e l c h e c k s u m . . . 1 b y t e 2 b y t e s 1 b y t e 1 b y t e 1 b y t e 2 b y t e s p a c k e t f o o t e r p a c k e t h e a d e r v a r i a b l e s i z e p a y l o a d ( f i r s t t h r e e p i x e l s i n n i n e b y t e s ) 8 b 8 b 8 b 8 b 8 b 8 b 8 b 8 b 8 b 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e v a r i a b l e s i z e p a y l o a d ( l a s t t h r e e p i x e l s p a c k e d i n n i n e b y t e s ) 8 b 8 b 8 b 8 b 8 b 8 b 8 b 8 b 8 b 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e 1 b y t e p i x e l 1 p i x e l 2 p i x e l 3 p i x e l n - 2 p i x e l n - 1 p i x e l n 0 r 0 7 r 7 0 g 0 7 g 7 0 b 0 1 b y t e 1 b y t e p i x e l 1 7 b 7 1 b y t e 8 b 8 b 8 b . . . 6 0 0 0 0 0 0 0 5 5 7 1 7 7 1 5 1 5 1 5 1 5 0 0 t i m e t i m e
LG4572B ver. 1.0. 4 lge confidential 62 figure 41 . non - burst mode with sync pulses figure 42 . non - burst mode with sync events a c t i v e v i d e o a r e a v s s h s s h s e r g b h s s h s e r g b . . . t l * ( v s a + v b p + v a c t + v f p ) t h b p t h s a t h a c t t h f p t l v s a l i n e s v b p l i n e s v f p l i n e s v a c t l i n e s h s s h s e b l l p t l v s s b l l p . . . t l b l l p t l h s s h s e b l l p t l . . . h s s h s e b l l p t l h s s h s e t l b l l p . . . h s s h s e t l b l l p h s s h s e t l b l l p l p m h s e h s e h s a h s a h s a h s a h s a h s a h s a h s a h s a h b p h f p h f p h b p h s a v s e a c t i v e v i d e o a r e a v s s b l l p h s s b l l p h s s b l l p h s s b l l p . . . h s s b l l p . . . h s s r g b h s s r g b . . . t l t l t l t l t l t l * ( v s a + v b p + v a c t + v f p ) t h b p t h a c t t h f p t l v s a l i n e s v b p l i n e s v a c t l i n e s h s s b l l p h s s b l l p . . . l p m v s s t l t l v f p l i n e s h s s t l b l l p h b p h f p h f p h b p
LG4572B ver. 1.0. 4 lge confidential 63 figure 43 . burst mode a c t i v e v i d e o a r e a v s s b l l p h s s b l l p h s s b l l p h s s b l l p . . . h s s b l l p . . . h s s r g b h s s r g b . . . t l t l t l t l t l t l * ( v s a + v b p + v a c t + v f p ) t h b p t h a c t t h f p t l v s a l i n e s v b p l i n e s v a c t l i n e s b l l p b l l p h s s b l l p h s s b l l p . . . l p m v s s t l t l v f p l i n e s h s s t l b l l p h b p h b p h f p h f p
LG4572B ver. 1.0. 4 lge confidential 64 5.7 mddi the lg 4572b supports mddi interface. the physical layer of mddi is based on a high - speed differential signaling. both command and image da ta transfer can be achieved with mddi. mddi host & client are linked by data and stb line. through data line, either command or image data is transferred from mddi host to mddi client, and vice versa. data is transferred by packet unit. through stb line, strobe signal is transferred. when the link is in ? forward direction , data is transferred from host to client, in reverse direction , client transfers data to mddi host. figure 44 . mddi transmitte r and receiver interface 5.7.1 mddi data and stb data is encoded using data - stb method. data signal is bi - direction over a pair of differential cable while stb signal in uni - directional over a pair of differential cable driven by a host as shown in the followi ng figure, which illustrates how the data sequence 11_1000_1011 is transmitted using data - stb encoding. figure 45 . mddi data - stb encoding q u a l c o m b a s e b a n d p r o c e s s o r c o n t a i n i n g h s t r a n s m i t t e r a n d h s r e c e i v e r l g 4 5 7 2 b w i t h h s r e c e i v e r a n d h s t r a n s m i t t e r d a t a 1 p d a t a 1 n c l k p c l k n d a t a 0 p d a t a 0 n m d d i _ d a t a 1 + m d d i _ s t b + m d d i _ s t b - h i g h s p e e d d a t a l i n k s ( l a n e 0 m a y b e b i d i r e c t i o n a l i n h s m o d e ) m d d i _ d a t a 1 - m d d i _ d a t a 0 + m d d i _ d a t a 0 - d a t a s t b r e c o v e r e d c l k
LG4572B ver. 1.0. 4 lge confidential 65 the below figure shows a exemplary circuit to show how to generate out data and recovered clock from host side data and stb signals. figure 46 . data and stb generation & recovery circuits the data and stb signals are always operated in a differential mode to maximize noise immunity . each differential pair is parallel terminated with the characteristic impedance of the cable. all parallel terminations are in the client device. figure below illustrate the configuration of the drivers, receivers , and terminati ons. the driver of each signal pair has a differential current output. while receiving mddi packets, the mddi_data and mdd_stb pairs use a conventional differential receiver with a differential voltage threshold of zero volts. in the hibernation state, the driver outputs are disabled and the parallel termination resistors pull the differential voltage on each signal pair to zero volts. during hibernation, a special receiver on the mddi_data pairs has an offset input differential voltage threshold of positiv e 125mv, which cause the hibernation line receiver interpret the un - driven signal pair as logic - zero level. figure 47 . differential connection between host and client d q d q d e l a y d q d q 0 1 o u t p u t d a t a [ 1 : 0 ] r e c o v e r e d c l o c k m d d i _ d a t a 0 + m d d i _ d a t a 0 - m d d i _ s t b + m d d i _ s t b - i n p u t d a t a i n p u t c l o c k h o s t c a b l e c l i e n t v t = 0 s t b e n a b l e h o s t - c l i e n t _ d a t a v t = 0 v t = 1 2 5 m v c l i e n t - h o s t _ d a t a c l i e n t - h o s t _ w a k e - u p v t = 0 v t = 1 2 5 m v h o s t c l i e n t s t b e n a b l e h o s t - c l i e n t _ d a t a c l i e n t - h o s t _ d a t a h o s t - c l i e n t _ w a k e - u p r t e m r t e m m d d i _ s t b + m d d i _ s t b - m d d i _ d a t a 0 + m d d i _ d a t a 0 -
LG4572B ver. 1.0. 4 lge confidential 66 5.7.2 mddi packet mddi transfer data i n a packet format. mddt host can generate and send packets. in lg 4572b , several packet format are supported. packets are transferred from mddi host to client(forward direction). burst reverse encapsulation packet is transferred from mddi client to host( rev erse direction). a number of packets, started by sub - frame header packet, construct 1 sub frame. figure 48 . mddi packet structure referring to mddi packet structure, sub - frame header packet is plac ed in front of a sub - frame, and some sub - frame construct media - frame together. table 7 . types of packets supported by lg 4572b packet function direction sub - frame header packet header of each sub frame forward register access pac ket register setting forward video stream packet video data transfer forward windowless video stream packet video data transfer forward filler packet fill empty packet space forward reverse link encapsulation packet reverse data packet reverse round - t rip delay measurement packet host ? ? sub - frame header packet figure 49 . sub - frame header packet structure p a c k e t l e n g t h p a c k e t t y p e u n i q u e w o r d s u b - f r a m e h e a d e r p a r a m e t e r s c r c v i d e o , a u d i o , s t a t u s , a n d c o m m a n d p a c k e t s s u b - f r a m e 0 s u b - f r a m e 1 s u b - f r a m e n - 1 s u b - f r a m e h e a d e r p a c k e t s u b - f r a m e n > 0 m e d i a - f r a m e ( a l s o o n e v i d e o f r a m e ) p a c k e t l e n g t h p a c k e t t y p e = 3 b f f h u n i q u e w o r d = 0 0 5 a h r e s e r v e d 1 s u b - f r a m e l e n g t h p r o t o c o l v e r s i o n s u b - f r a m e c o u n t m e d i a f r a m e c o u n t c r c 2 b y t e s 2 b y t e s 2 b y t e s 2 b y t e s 4 b y t e s 2 b y t e s 2 b y t e s 4 b y t e s 2 b y t e s p a c k e t l e n g t h : p a c k e t l e n g t h n o t i n c l u d i n g p a c k e t l e n g t h b l o c k p a c k e t t y p e : p a c k e t t y p e ( s u b - f r a m e h e a d e r p a c k e t i s 3 b f f h ) u n i q u e w o r d : i d e n t i f y t h i s p a c k e t i s s u b - f r a m e h e a d e r p a c k e t r e s e r v e d 1 : n o t u s e d ( s e t z e r o ) p r o t o c o l v e r s i o n : s e t a l l z e r o s u b - f r a m e c o u n t : s p e c i f i e s n u m b e r o f s u b - f r a m e h e a d e r p a c k e t s m e d i a f r a m e c o u n t : s p e c i f i e s n u m b e r o f m e d i a f r a m e s c r c : e r r o r c h e c k
LG4572B ver. 1.0. 4 lge confidential 67 register access packet figure 50 . register access packet structure video st ream packet figure 51 . video stream packet structure filler packet figure 52 . filler packet structure p a c k e t l e n g t h p a c k e t t y p e = 1 4 6 b c l i e n t i d r e a d / w r i t e i n f o r e g i s t e r a d d r e s s p a r a m e t e r c r c r e g i s t e r d a t a l i s t r e g i s t e r d a t a c r c 2 b y t e s 2 b y t e s 2 b y t e s 2 b y t e s 4 b y t e s 2 b y t e s p a c k e t l e n g t h C 1 4 b y t e s 2 b y t e s p a c k e t l e n g t h : p a c k e t l e n g t h n o t i n c l u d i n g p a c k e t l e n g t h b l o c k p a c k e t t y p e : p a c k e t t y p e ( r e g i s t e r a c c e s s p a c k e t i s 1 4 6 ( d e c i m a l ) ) b c l i n e t i d : s e t t o a l l z e r o r e a d / w r i t e i n f o : t o w r i t e r e g i s t e r v a l u e , b i t s [ 1 5 : 1 4 ] = 0 0 t o r e a d r e g i s t e r v a l u e , b i t s [ 1 5 : 1 4 ] = 1 0 b i t [ 1 3 : 0 ] r e f e r t o v e s a s p e c r e g i s t e r a d d r e s s : r e g i s t e r a d d r e s s i s w r i t t e n h e r e p a r a m e t e r c r c : t o c h e c k e r r o r f r o m p a c k e t l e n g t h t o r e g i s t e r a d d r e s s r e g i s t e r d a t a l i s t : a l i s t o f 4 b y t e r e g i s t e r d a t a v a l u e s t o b e w r i t t e n t o l d i r e g i s t e r d a t a c r c : t o e r r o r c h e c k r e g i s t e r d a t a l i s t * b a s i s o f r e g i s t e r d a t a l i s t i s 4 - b y t e u n i t . t h e r e f o r e , w h e n r e g i s t e r p a r a m e t e r i s n o t m u l t i p l y o f 4 . r e m a i n d e r b i t s m u s t f i l l b y 0 . p a c k e t l e n g t h p a c k e t t y p e = 1 6 b c l i e n t i d v i d e o d a t a f o r m a t d e s c r i p t o r p i x e l d a t a a t t r i b u t e s x l e f t e d g e y b o t t o m e d g e 2 b y t e s 2 b y t e s 2 b y t e s 2 b y t e s 2 b y t e s 2 b y t e s 2 b y t e s p a c k e t l e n g t h : p a c k e t l e n g t h n o t i n c l u d i n g p a c k e t l e n g t h b l o c k p a c k e t t y p e : p a c k e t t y p e ( v i d e o s t r e a m p a c k e t i s 1 6 ( d e c i m a l ) ) b c l i n e t i d : s e t t o a l l z e r o v i d e o d a t a f o r m a t d e s c r i p t o r b i t s [ 1 5 : 1 3 ] = 0 1 0 : r a w r g b f o r m a t ( f i x e d v a l u e ) b i t [ 1 2 ] = 1 : o n l y p a c k e d t y p e i s a v a i l a b l e ( f i x e d v a l u e ) b i t s [ 1 1 : 0 ] = 1 0 0 0 _ 1 0 0 0 _ 1 0 0 0 : 2 4 b i t p i x e l b i t s [ 1 1 : 0 ] = 0 1 1 0 _ 0 1 1 0 _ 0 1 1 0 : 1 8 b i t p i x e l b i t s [ 1 1 : 0 ] = 0 1 0 1 _ 0 1 1 0 _ 0 1 0 1 : 1 6 b i t p i x e l p i x e l d a t a a t t r i b u t e s b i t s [ 1 : 0 ] = 1 1 : d i s p l a y e d b o t h e y e s ( f i x e d v a l u e ) b i t s [ 5 ] = 1 : x l e f t e d g e , y s t a r t e d g e i s n o t d e f i n e d ( f i x e d v a l u e ) o t h e r b i t s a r e a l l z e r o x l e f t e d g e : x c o o r d i n a t e o f t h e l e f t e d g e o f t h e s c r e e n w i n d o w f i l l e d b y t h e p i x e l d a t e f i e l d . y t o p e d g e : y c o o r d i n a t e o f t h e t o p e d g e o f t h e s c r e e n w i n d o w f i l l e d b y t h e p i x e l d a t e f i e l d . x r i g h t e d g e : x c o o r d i n a t e o f t h e r i g h t e d g e o f t h e w i n d o w b e i n g u p d a t e d . y b o t t o m e d g e : y c o o r d i n a t e o f t h e b o t t o m e d g e o f t h e w i n d o w b e i n g u p d a t e d . x s t a r t : x s t a r t p i x e l a d d r e s s . y s t a r t : y s t a r t p i x e l a d d r e s s . p i x e l c o u n t : w r i t e n u m b e r o f p i x e l p a r a m e t e r c r c : t o c h e c k e r r o r f r o m p a c k e t l e n g t h t o p i x e l c o u n t p i x e l d a t a : p i x e l d a t a i n f o . n u m b e r o f p i x e l d a t a m u s t n o t b e o v e r 6 5 5 0 9 p i x e l d a t a c r c : t o e r r o r c h e c k p i x e l d a t a y t o p e d g e x r i g h t e d g e y s t a r t 2 b y t e s x s t a r t p a r a m e t e r c r c p i x e l c o u n t p i x e l d a t a p i x e l d a t a c r c 2 b y t e s 2 b y t e s 2 b y t e s 2 b y t e s 2 b y t e s p a c k e t l e n g t h C 2 6 b y t e s 2 b y t e s p a c k e t l e n g t h p a c k e t t y p e = 0 f i l l e r b y t e s ( a l l z e r o ) c r c 2 b y t e s 2 b y t e s p a c k e t l e n g t h C 1 4 b y t e s 2 b y t e s p a c k e t l e n g t h : p a c k e t l e n g t h n o t i n c l u d i n g p a c k e t l e n g t h b l o c k p a c k e t t y p e : p a c k e t t y p e ( f i l l e r p a c k e t i s 0 ( d e c i m a l ) ) f i l l e r b y t e s : s e t t o a l l z e r o ( t h e s i z e i s u n d e r p a c k e t l e n g t h a v a i l a b l e ) c r c : t o e r r o r c h e c k
LG4572B ver. 1.0. 4 lge confidential 68 link shutdown packet figure 53 . link shutdown packet structure 5.7.3 write and read sequences with mddi packet lg 4572b supports video stream packet for memory write and register access packet for register w rite/read. followings are the examples of memory and register write/read sequence s . write video data figure 54 . video data write sequence table 8 . color mode setting in mddi video data format descriptor[11:0] colo r mode 1000_1000_1000 24 bits/ pixel 0110_0110_0110 18 bits/ pixel 0101_01 10 _0101 16 bits/ pixel p a c k e t l e n g t h p a c k e t t y p e = 6 9 c r c 2 b y t e s 2 b y t e s 2 b y t e s p a c k e t l e n g t h : p a c k e t l e n g t h n o t i n c l u d i n g p a c k e t l e n g t h b l o c k p a c k e t t y p e : p a c k e t t y p e ( l i n k s h u t d o w n p a c k e t i s 6 9 ( d e c i m a l ) ) c r c : t o e r r o r c h e c k a l l z e r o s : w r i t e a l l z e r o ( s i z e i s 1 6 b y t e s ) a l l z e r o s 1 6 b y t e s s u b f r a m e h e a d e r p a c k e t c o l o r m o d e s e t t i n g ( r e g i s t e r a c c e s s p a c k e t ) v i d e o d a t a t r a n s f e r ( v i d e o s t r e a m p a c k e t ) v i d e o d a t a t r a n s f e r ( v i d e o s t r e a m p a c k e t ) v i d e o d a t a t r a n s f e r ( v i d e o s t r e a m p a c k e t ) r 3 r 4 r 5 r 6 r 7 g 2 g 3 g 4 g 5 g 6 g 7 b 4 b 3 b 2 b 1 b 0 r 2 b 5 p i x e l 1 b l u e p i x e l 1 g r e e n p i x e l 1 r e d 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 m d d i b y t e n m d d i b y t e n + 1 m d d i b y t e n + 2 b 7 b 6 g 0 g 1 r 0 r 1
LG4572B ver. 1.0. 4 lge confidential 69 figure 55 . 24bits/pixel(b:8, g:8, r:8) data transfer format figure 56 . 18bits/pixel(b:6, g:6, r:6) ) data transfer format figure 57 . 16bits/pixel(b:5, g:6, r:5) ) data transfer format write register figure 58 . writing register sequence read video data from memory in order to read a pixel data from memory(readable one pixel only), the following sequence should be programmed. memory read command (2eh) is followed by reverse encapsulation packet. ddi t ransmits video pixel data through encapsulation packet. please refer to vesa spec for detailed description. 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 m d d i b y t e n + 3 m d d i b y t e n + 4 m d d i b y t e n + 5 p i x e l 2 b l u e p i x e l 2 g r e e n p i x e l 2 r e d r 3 r 4 r 5 r 6 r 7 g 2 g 3 g 4 g 5 g 6 g 7 b 4 b 3 b 2 b 1 b 0 r 2 b 5 b 7 b 6 g 0 g 1 r 0 r 1 p i x e l 1 b l u e p i x e l 1 g r e e n p i x e l 1 r e d p i x e l 2 b l u e 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 m d d i b y t e n m d d i b y t e n + 1 m d d i b y t e n + 2 b 4 b 3 b 2 b 1 b 0 b 5 r 3 r 4 r 5 r 2 r 0 r 1 b 4 b 3 b 2 b 1 b 0 b 5 g 2 g 3 g 4 g 5 g 0 g 1 p i x e l 2 g r e e n p i x e l 2 r e d p i x e l 3 b l u e p i x e l 3 g r e e n 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 m d d i b y t e n + 3 m d d i b y t e n + 4 m d d i b y t e n + 5 g 2 g 3 g 4 g 5 g 0 g 1 r 3 r 4 r 5 r 2 r 0 r 1 b 4 b 3 b 2 b 1 b 0 b 5 g 2 g 3 g 4 g 5 g 0 g 1 p i x e l 1 b l u e p i x e l 1 g r e e n p i x e l 1 r e d p i x e l 2 b l u e p i x e l 2 g r e e n 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 m d d i b y t e n m d d i b y t e n + 1 m d d i b y t e n + 2 g 2 g 3 g 4 g 5 g 0 g 1 r 3 r 4 r 2 r 0 r 1 b 4 b 3 b 2 b 1 b 0 g 2 g 0 g 1 b 4 b 3 b 2 b 1 b 0 p i x e l 2 r e d p i x e l 3 b l u e p i x e l 3 g r e e n 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 0 1 2 3 4 6 7 5 m d d i b y t e n + 3 m d d i b y t e n + 4 m d d i b y t e n + 5 p i x e l 3 r e d g 3 g 4 g 5 r 3 r 4 r 2 r 0 r 1 b 4 b 3 b 2 b 1 b 0 g 2 g 3 g 4 g 5 g 0 g 1 r 3 r 4 r 2 r 0 r 1 p i x e l 2 g r e e n sub frame header packet command transfer ( register access packet )
LG4572B ver. 1.0. 4 lge confidential 70 figure 59 . read video data from memory read register values in order to read registers, the following sequence should be programmed. register read command is followed by reverse encapsulation packet. ddi transmits register data through encapsulation packet. please refer to vesa spec for detailed description. figure 60 . read register note : only level 1 registers are readable in mddi. note : not only level 1 register (ex. d5h) 5.7.4 tearing - less display in lg 4572b , the ma tching between data writes timing and written data display timing is important. if timing is mismatched, tearing effect can occur. to avoid display tearing effect, two possible ways are suggested. first case is that data write is slower than the speed of displaying written data as shown in the following figure. for this case, data write speed is not critical, but current consumption in interface will be increased because data transfer time is long. data write time is selected widely in this case. s u b f r a m e h e a d e r p a c k e t r e a d m e m o r y ( 2 e h ) t r a n s f e r ( r e g i s t e r a c c e s s p a c k e t ) r e v e r s e e n c a p s u l a t i o n t r a n s f e r ( r e v e r s e e n c a p s u l a t i o n p a c k e t ) s u b f r a m e h e a d e r p a c k e t r e a d r e g i s t e r c o m m a n d t r a n s f e r ( r e g i s t e r a c c e s s p a c k e t ) r e v e r s e e n c a p s u l a t i o n t r a n s f e r ( r e v e r s e e n c a p s u l a t i o n p a c k e t )
LG4572B ver. 1.0. 4 lge confidential 71 figure 61 . tearing - less display : display speed is faster than data write speed. other case is that data write is faster than the speed of displaying written data as shown in the following figure. for t his case, data update speed is very high so that transfer time is to avoid data scan conflicts with data update. figure 62 . tearing - less display : display speed is slower than data write speed. 5.7.5 hibernat ion and wakeup the lg 4572b support s hibernation mode to save interface power consumption. mddi link can enter the hibernation state quickly and wake up from hibernation quickly. this allows the system to force mddi link into hibernation frequently to save power consumption. during hibernation mode, the hi - speed transmitters and receivers are disabled and low - speed & low - power receivers are enabled in order detect wake - up sequence. b p b p f p f p m d d i _ f r a m e _ c k f i r s t f r a m e s e c o n d f r a m e t h i r d f r a m e w k l f r a m e u p d a t e 4 8 0 d a t a u p d a t e l i n k w a k e u p w k l i s t o s e t l a t e r t h a n d a t a s c a n a n d c o n s i d e r t h a t d a t a w r i t e i s t o b e c o m p l e t e d b e f o r e n e x t d a t a s c a n i s c o m p l e t e d . d a t a s c a n d a t a w r i t e b p b p f p f p m d d i _ f r a m e _ c k f i r s t f r a m e s e c o n d f r a m e t h i r d f r a m e w k l f r a m e _ u p d a t e 4 8 0 d a t a u p d a t e l i n k w a k e u p w k l i s t o s e t p r e v i o u s l y t h a n d a t a s c a n a n d c o n s i d e r t h e t i m e t h a t r e v e r s e t i m e f r o m c l i e n t t o h o s t t o s e n d r e q u e s t s i g n a l . d a t a s c a n d a t a w r i t e
LG4572B ver. 1.0. 4 lge confidential 72 figure 63 . mddi tran sceiver and receiver ? s states in hibernation when the link wakes up from hibernation, the host and client exchange a sequence of pulses. these pulses can be detected using low - speed, low - power receivers that consume only a fraction of the current of the d ifferential receivers required to receive the signals at the maximum link operating speed. either the client or the host can wake up the link; host - initiated link wakeup. host - initiated link wake - up procedure the simple case of host - initiated wake - up is described below without contention from the client trying to wake up at the same time. the following sequence of events is illustrated in the following figure. figure 64 . host - initiated link wake - up s equence 1. the host sends a link shutdown packet to inform the client that the link will transition to the low - s t b ( h o s t ) e n a b l e ( h o s t ) ( h o s t t o c l i e n t ) d a t a ( c l i e n t t o h o s t ) d a t a ( c l i e n t t o h o s t ) w a k e - u p ( c l i e n t t o h o s t ) d a t a ( h o s t t o c l i e n t ) w a k e - u p s t b ( c l i e n t ) ( h o s t t o c l i e n t ) d a t a e n a b l e ( c l i e n t ) m d d i s t b + m d d i s t b - m d d i d a t a + m d d i d a t a - h o s t c l i e n t o f f o f f o f f o f f o f f o f f o n o n v t = 0 v t = 1 2 5 m v v t = 1 2 5 m v r t e r m r t e r m l i n k s h u t d o w n p a c k e t m d d i _ d a t a s u b - f r a m e h a r d e r p a c k e t m d d i _ s t b 1 7 6 5 4 3 2 l a s t f o r w a r d t r a f f i c 6 4 s t b p u l s e s h o s t d i s a b l e s d a t a a n d s t b d r i v e r s h o s t b e g i n s l i n k r e s t a r t w i t h m d d i _ d a t a h i g h f o r 1 5 0 s t b p u l s e s c l i e n t d o e s n o t d r i v e m d d i _ d a t a h o s t d r i v e s l o g i c - z e r o l e v e l f i r s t f o r w a r d t r a f f i c h i b e r n a t i o n 1 5 0 p u l s e s 5 0 p u l s e s
LG4572B ver. 1.0. 4 lge confidential 73 power hibernation state. 2. following the crc of the link shutdown packet the host toggle mddi_stb for 64 cycles to allow processing in the cli ent to finish before it stops mddi_stb from toggling which stops the recovered clock in the client device. also during this interval the host initially sets mddi_data to a logic_zero level, and then disables the mddi_data output in the range of 16 to 48 m ddi_stb cycles(including output disable propagation delays) after the crc. it may be desirable for the client to place its high - speed receivers for mddi_data and mddi_stb into a low power state any time after 48 mddi_stb cycles after the crc and before po int 3. 3. the host enters the low - power hibernation state by disabling the mddi_data and mddi_stb drivers and by placing the host controller into a low - power hibernation state. it is also allowable for mddi_stb to be driven to logic_zero level or to conti nue toggling during hibernation. the client is also in the low - power hibernation state. 4. after a while, the host begins the link restart sequence by enabling the mddi_data and mddi_stb driver outpu ts . the host drive s mddi_data to a logic - one level and m ddi_stb to logic - zero level for at least the time it takes for the drivers to fully enable their outputs. the host shall wait at least 200 nsec after mddi_data reaches a valid logic - one level and mddi_stb reaches a valid logic - zero level before driving pu lses on mddi_stb. this gives the client sufficient time to prepare to receive high - speed pulses on mddi_stb. the client first detects the wake - up pulse using a low - power differential receiver having a +125mv input offset voltage. 5. the host drive rs are f ully enabled and mddi_data is being driven to a logic - one level. the host begins to toggle mddi_stb in a manner consistent with having logic - zero level on mddi_data for duration of 150 mddi_stb c y c les. 6. the host drive s mddi_data to logic - zero level fo r 50 mddi_stb cycles. the client begins to look for the sub - frame header packet after mddi_data is at logic - zero level for 40 mddi_stb cycles. 7. the host begins to transmit data on the forward link by sending a sub - frame header packet. beginning at poin t 7. the mddi host generates mddi_stb based on the logic level on mddi_data so that proper data - strobe encoding commences from point 7. vsync based host - initiated link wake - up procedure in display - on state, when the ic finishes displaying all internal gra m data, data request must be transferred to mddi host for new video data. as mddi link is usually in hibernation for reducing interface power consumption, mddi link wake - up must be done before internal gram update. in that case, client initiated link wake - up can be used as data request. when vsync based link wake - up register(e0h: vwake_en) is set, client initiated wake - up is executed in synchronization with the vertical - sync signal which generated in lg 4572b . using vsync based link wake - up, tearingless di splay can be accomplished if interface speed and wake - up time is well known. the following figure shows detailed timing for vsync based link wake - up.
LG4572B ver. 1.0. 4 lge confidential 74 figure 65 . vsync based host - initiated link wake - u p sequence the detailed description for labeled events as follows: 1. mddi host writes to the vsync based link wakeup register to enable a wake - up based on internal vertical - sync signal. 2. link_active goes low when the host puts in the link into hibern ation after no more data needs to be sent to the lg 4572b . 3. frame_update, the internal vertical - sync signal goes high indicating that update pointer has wrapped around and is now reading from the beginning of the frame buffer. link wake - up can be set usi ng wkf and wkl(e1h) registers. wkf specifies the number of frame before wake - up; wkl specifies the number of lines before wake - up 4. client_wakeup input to the mddi client goes high to start the client initiated link wake - up. 5. link_active goes high aft er the host brings the link out of hibernation. 6. after link wake - up, client_wakeup signal and the vwake_en register are cleared automatically. client - initiated link wake - up procedure an example of a typical client - initiated service request event with no contention is illustrated in the following figure. figure 66 . client - initiated link wake - up sequence the detailed description for labeled events are as follows; 1. the host sends a link shutdown packet to inform the client that the link will transition to the low - power hibernation state. 2. following the crc of the link shutdown packet the host toggles mddi_stb for 64 cycles to allow processing in the client to finish before it stops mddi_stb from toggling which stops the recovered v w a k e _ e n l i n k _ a c t i v e f r a m e _ u p d a t e c l i e n t _ w a k e u p 1 2 3 4 5 6 s y n c s t a t e h i b e r n a t i o n s t a t e w a k e _ u p s t a t e s y n c s t a t e l i n k s h u t d o w n p a c k e t m d d i _ d a t a s u b - f r a m e h a r d e r p a c k e t m d d i _ s t b 1 7 6 5 4 3 2 l a s t f o r w a r d t r a f f i c 6 4 s t b p u l s e s h o s t d i s a b l e s d a t a a n d s t b d r i v e r s h o s t r e s p o n d s b y d r i v i n g a l o g i c _ z e r o l e v e l t h e n c l i e n t s t o p s d r i v i n g m d d i _ d a t a h o s t d r i v e s l o g i c - z e r o l e v e l f i r s t f o r w a r d t r a f f i c h i b e r n a t i o n 8 0 p u l s e s 5 0 p u l s e s 7 0 p u l s e s c l i e n t b e g i n s l i n k r e s t a r t d r i v e s m d d i _ d a t a h i g h < 1 m s e c < 1 0 0 n s e c 8 9
LG4572B ver. 1.0. 4 lge confidential 75 clock in the client device. also during this interval the host initially sets mddi_data to a logic_zero level, and then disables the mddi_data output in the range of 16 to 48 mddi_stb cycles(including output disable prop agation delays) after the crc. it may be desirable for the client to place its high - speed receivers for mddi_data and mddi_stb into a low power state any time after 48 mddi_stb cycles after the crc and before point 3. 3. the host enters the low - power hibe rnation state by disabling the mddi_data and mddi_stb drivers and by placing the host controller into a low - powre hibernation state. it is also allowable for mddi_stb to be driven to logic_zero level or to continue toggling during hibernation. the client i s also in the low - power hibernation state. 4. after a while, the client begins the link restart sequence by enabling the mddi_stb receiver and also enabling an offset in its mddi_stb receiver to guarantee the state of the received version of mddi_stb is a logical - zero level in the client before the host enables its mddi_stb driver. the client will need to enable the offset in mddi_stb immediately before enabling its mddi_stb receiver to ensure that mddi_stb receiver in the client is always receiving a vali d differential signal and to prevent erroneous received signals from propagation into the client. after that, the client enables its mddi_data driver while driving mddi_data to a logic - one level. it is allowed for mddi_data and mddi_stb to be enabled simu ltaneously if the time to enable the offset and enable the standard mddi_stb differential receiver is less than 200 nsec. 5. within 1 msec the host recognizes the service request pulse, and the host begins the link restart sequence by enabling the mddi_da ta and mddi_stb driver output. the host drivers mddi_data to a logic - one level and mddi_stb to a logic - zero level for at least the time it takes for the drivers to fully enable their outputs. the host shall wait at least 200 nsec after mddi_data reaches a valid logic - one level and mddi_stb reaches a valid fully - driven logic - zero level before diving pulses on mddi_tsb. this gives the client sufficient time to prepare to receive high - speed pulses on mddi_stb. 6. the host begins outputting pulses on mddi_stb and shall keep mddi_data at a logic - one level for a total duration of 150 mddi_stb pulses through point 8. the host generates mddi_stb in a manner consistent with sending a logical - zero level on mddi_data. when the client recognizes the first pulse on mddi _stb it shall disable the offset in its mddi_stb receiver. 7. the client continues to drive mddi_data to a logic - one level for 70 mddi_stb pulses, and the client disables its mddi_data driver at point 7. the host continues to drive mddi_data to a logic - on e level for duration of 80 additional mddi_stb pulses, and at point 8 drivers mddi_data to logic - zero level. 8. the host drivers mddi_data to logic - zero level for 50 mddi_stb cycles. the client begins to look for the sub - frame header packet after mddi_dat a is at logic - zero level for 40 mddi_stb cycles. 9. after asserting mddi_data to logic - zero level and driving mddi_stb for duration of 50 mddi_stb pulses the host begins to transmit data on the forward link at point 9 by sending a sub - frame header packet. the client begins to look for the sub - frame header packet after mddi_data is at logic - zero level for 40 mddi_stb cycles. 5.7.6 mddi operation modes in mddi, 6 operation modes are available. the following table describes 6 modes.
LG4572B ver. 1.0. 4 lge confidential 76 table 9 . color mode setting in mddi state oscillator step - up internal logic status mddi io wake - up by init_hiber off disable display off internal logic on mddi link hibernation h ibernation driver on host - initiated wait off disable display off internal logic on mddi link sync standard driver on - normal on enable display on internal logic on mddi link sync standard driver on - hiber on enable display on internal logic on mddi link hibernation h ibernation driver on host - initiated client - initiated (vsync) sl eep off disable display off internal logic on mddi link sync standard driver on - stop off disable display off internal logic on mddi link off driver all off reset init_hiber : initial status when external power is connected to the ic. in this state, in ternal o scillator is off, and mddi link is hibernation state. as no command or signal is applied to the ic except reset input and booster circuit is off, and internal logic is on. w ait : after the wake - up sequence, the ic is in wait state. mddi link is in sync, and internal logic is on, and booster is still off because no other register access or video stream packet is transferred to the ic. normal : mddi link, booster circuit, and internal logic circuit are on. register access or video data transfer is a vailable in normal state. hiber : when no more video data update is needed, mddi link is in hibernation so that interface power can be reduced. internal booster & logic circuits are still operating. mddi link wakeup will be accomplished when vsync wakeup r egister is set before hibernation. sleep : this state is set by register access. booster is off, but mddi link and internal logic have to be in sync because the ic must receive commands for power save or normal operation. stop : stop state is set by mddi_s lp register access(e0h). in this state, mddi link, internal oscillator, booster are all off and internal logic is still on. to release stop state, input reset signal. after reset, status is init_hiber state.
LG4572B ver. 1.0. 4 lge confidential 77 figure 67 . operating state in mddi modes p o w e r o n i n i t _ h i b e r w a i t n o r m a l s l e e p h i b e r s y t e m p o w e r o n - o s c : o s c o f f - s t e p - u p : d i s a b l e d - m d d i l i n k : h i b e r n a t i o n - l o g i c : d i s p l a y o f f - o s c : o s c o f f - s t e p - u p : d i s a b l e d - m d d i l i n k : i n s y n c - l o g i c : d i s p l a y o f f - o s c : o s c o n - s t e p - u p : e n a b l e d - m d d i l i n k : i n s y n c - l o g i c : d i s p l a y o n s y s t e m r e s e t i n p u t m d d i l i n k s y n c h r o n i z a t i o n p r o c e d u r e 1 ) p o w e r s e t t i n g u s i n g r e g i s t e r p a c k e t 2 ) s t e p - u p e n a b l e s e q u e n c e u s i n g r e g i s t e r p a c k e t 3 ) f r a m e b u f f e r a c c e s s u s i n g v i d e o p a c k e t 4 ) d i s p l a y o n s e q u e n c e u s i n g r e g i s t e r p a c k e t - o s c : o s c o f f - s t e p - u p : d i s a b l e d - m d d i l i n k : i n s y n c - l o g i c : d i s p l a y o f f - o s c : o s c o n - s t e p - u p : e n a b l e d - m d d i l i n k : h i b e r n a t i o n - l o g i c : d i s p l a y o n - s t o p s t a t e s e t t i n g u s i n g r e g i s t e r p a c k e t ( b o t h s t a n d a r d & o f f s e t r e c e i v e r d i s a b l e d ) s t o p - o s c : o s c o f f - s t e p - u p : d i s a b l e d - m d d i l i n k : l i n k d i s a b l e d - l o g i c : d i s p l a y o f f m d d i l i n k w a k e - u p ! - v s y n c w a k e u p - g p i o w a k e u p - h o s t i n i t i a t e d w a k e u p o n l y r e s e t s i g n a l i s a d m i t t e d f o r w a k e - u p f r o m s t o p s t a t e ! s l e e p s t a t e s e t s e q u e n c e 1 ) d i s p l a y o f f s e q u e n c e u s i n g r e g i s t e r p a c k e t ( o p t i o n a l ) 2 ) s l e e p s t a t e s e t t i n g ( s l p i n = 1 0 h ) u s i n g r e g i s t e r p a c k e t s l e e p s t a t e r e l e a s e s e q u e n c e 1 ) s l p o u t ( 1 1 h ) c o m m a n d s e t t i n g 2 ) s t e p - u p e n a b l e s e q u e n c e 3 ) f r a m e b u f f e r u p d a t e ( o p t i o n a l ) 4 ) d i s p l a y o n s e q u e n c e h i b e r s t a t e ( w h e n f r a m e b u f f e r u p d a t e n o t n e e d e d ) 1 ) v s y n c w a k e u p e n a b l e r e g i s t e r s e t t i n g ( o p t i o n a l ) 2 ) l i n k s h u t - d o w n u s i n g l i n k s h u t - d o w n p a c k e t ( m d d i l i n k i s i n h i b e r n a t i o n s t a t e ) s t o p s t a t e 1 ) m d d i c t l 1 ( e 0 h ) m d d i _ s l p r e g i s t e r s e t t i n g 2 ) p r e v i o u s s t a t e i s w a i t o r n o r m a l o r s l e e p f o r e n t e r i n g t h i s s t a t e 1 2 3 4 4 3 1 2
LG4572B ver. 1.0. 4 lge confidential 78 5.8 backlight control function 5.8.1 cabc ( content adaptive brightness control ) the lg 4572b supports content adaptive brightness control function which can be used to reduce the power consumption of the luminan ce source. content adaptation means that content gray scale can be increased while simultaneously lowering brightness of the backlight to achieve same perceived brightness. the adjusted gray scale and thus the power consumption reduced depend on the conten t of the image. the following figure shows that how the cabc algorithm works. the cabc block accumulates the gray scales for each pixels of the image and thus cabc block comes to know the histograms about the gray scales of the image. next, cabc block mod ify the original image da ta to have more widely spread shape while it makes the back light luminance lower so that the image luminance perceived by human becomes almost the same. figure 68 . content ada ptive brightness control t h r e s h o l d ( e x : 9 0 % ) 6 0 . 9 % o p t i m a l b a c k l i g h t b r i g h t n e s s c o u n t n u m b e r a c c u m u l a t i v e t o t a l c o u n t 1 0 0 % 8 0 % 6 0 % 4 0 % 2 0 % 0 % t h r e s h o l d ( e x : 9 0 % ) 4 7 . 8 % o p t i m a l b a c k l i g h t b r i g h t n e s s a c c u m u l a t i v e t o t a l c o u n t 1 0 0 % 8 0 % 6 0 % 4 0 % 2 0 % 0 % c o u n t n u m b e r o p t i m a l b a c k l i g h t b r i g h t n e s s v a l u e c a n b e f o u n d b y h i s t o g r a m a n a l y s i s
LG4572B ver. 1.0. 4 lge confidential 79 5.8.2 brightness control block and cabc block figure 69 . block diagram for brightness control block and cabc block brightness control block is used to control the display brightness as follows: there is a resister, dbv: 8 bit, for display brightness of manual brightness setting and cabc in the display module. there is a pwm output signal, bc line, to control the led driver ic in order to control display brightness. the brightness con trol method should be taken into account to avoid abnormal visible effect related with scanning frame frequency. the brightness control block can be used in manual brightness mode and cabc mode, see write ctrl display (53h) and write content adaptive br ightness control (55h). the user can adjust brightness, see write display brightness (51h) for the display. wrcabc(55h) function rdcabcmb(5fh) image cabc off 00b disable wrcabcmb(5eh) original cabc on 01b /10b /11b enable wrcabcmb(5eh) cabc modified brightness level calculates with the following formula. display output brightness = manual brightness setting * cabc brightness ratio below drawing is for the explanation of the cabc minimum brightness setting. b r i g h t n e s s c o n t r o l b l o c k c o n t r o l b i t : b t c r l b t c r l = 0 : i n a c t i v e b t c r l = 1 : a c t i v e c a b c b l o c k d b v [ 7 . . 0 ] g a m m a c o n t r o l b l o c k s w m a n u a l b r i g h t n e s s s e t t i n g w r i t e d i s p l a y b r i g h t n e s s ( 5 1 h ) i m a g e d a t a b r i g h t n e s s d a t a b r i g h t n e s s d a t a c o n t r o l b i t : b l b l = 0 : i n a c t i v e b l = 1 : a c t i v e b c l e d b a c k l i g h t p r o c e s s e d i m a g e d a t a
LG4572B ver. 1.0. 4 lge confidential 80 figure 70 . contr olled display brightness by labc and cabc algorithm cabc minimum brightness value = 51 (33h: 20% display brightness) display brightness [manual setting] brightness ratio[cabc] calculation result of the display brightness formula display output brightness image case 1 50% 70% 35% 35% cabc modified case 2 20% 70% 14% 20% cabc modified case 3 50% 70% 35% 35% cabc modified at the case 2, the calculation result of the display brightness is 14%. cabc minimum brightness value is set to 20% brightness. actua l display brightness is 20% as the cabc minimum brightness setting. to get more easy understandings and control of this cabc function, the below conceptual control flow diagram would be a help. in the following diagram , the dd, bctrl, and bl are control p arameter in 53h register. they control the cabc paths. if dd=0, then cabc function is disabled and the manual brightness setting by dbv[7:0] in 51h register is available . if dd=1, cabc function will start to work with the maximum and minimum bright ness set tings respectively by dbv[7:0] and cmb[7:0] in 5eh register. if bctrl=1, the cabc function will go through to next path. but if bctrl=0, gnd level for blu_pwm would be forced. if bl=1, the cabc function will go though with bctrl=1 and controls the duties of pwm (pulse width modulated) waveforms through blu_pwm pad. finally, the pwmp parameter in c8h register can change the polarity of blu_pwm output. if pwmp=0, blu_pwm waveform works as active high but if 1, then the blu_pwm waveform works as active low. the not - shown parameter in the following diagram to control cabc function are cdsp[3:0], cdmp[3:0], and fpwm[1:0] in c8h register, where cdsp and cdmp parameter control the dimming levels of still images and moving images, respectively. if cdsp=8, then t he duties of blu_pwm are increased or decreased by 8 levels per frame, whose total levels of this is 255, after comparing the differences between predetermined threshold value and the calculated histogram value for still images. and if cdmp=4, then the dut ies of blu_pwm are increased or decreased by 4 levels per frame, whose total levels of this is 255, after comparing the differences between predetermined threshold value and the calculated histogram value for moving images. the last parameter fpwm controls the frequencies of blu_pwm output. the setting 0 means 2 times of frame frequency, 1 means 4 times, 2 means 8
LG4572B ver. 1.0. 4 lge confidential 81 times, and 3 means 16 times of frame frequency. it goes faster according to the increased fpwm values. the tables for them are shown in c8h regi ster description section. figure 71 . conceptual control flow diagram of cabc function. d d d b v [ 7 : 0 ] c a b c f u n c . 0 1 0 1 b c t r l 0 1 b l b l u _ p w m p w m p c m b [ 7 : 0 ] m a x . b r i g h t n e s s c o n t r o l . m i n . b r i g h t n e s s c o n t r o l .
LG4572B ver. 1.0. 4 lge confidential 82 5.9 lcd power supply circuit the lcd power supply circuit generates the voltage levels of ddvdh, ddvdl, vcl, vreg1 out, vreg2out, vgh, vgl, lvgl and vcom for driving an lcd. the internal logic power supply regulator generates internal logic power supply vdd. 5.9.1 voltage setting pattern diagram the pattern diagram of voltage setting and waveforms of the liquid crystal appli cation voltages are as follows. figure 72 . pattern diagram for voltage setting ( x 4 , x 5 , x 6 ) ( x - 1 ) ( x - 4 , x - 5 , x - 6 ) v g h ( < + 1 5 v ) v c l v g l ( > - 1 5 . 0 v ) g n d b t [ 2 : 0 ] b t [ 2 : 0 ] g n d ( 0 v ) i o v c c ( 1 . 6 5 v ~ 3 . 3 v ) v d d ( 1 . 4 0 v ~ 1 . 7 0 v ) v c i ( 2 . 6 v ~ 3 . 3 v ) v r e g 1 o u t v r e g 1 o u t ( < d d v d h - 0 . 5 v ) v c o m ( v r e g 2 o u t ~ 0 v ) v r h 1 [ 4 : 0 ] v r h 2 [ 4 : 0 ] v c m [ 6 : 0 ] v r e g 2 o u t ( > d d v d l + 0 . 5 v ) v r e g 2 o u t d d v d l ( - d d v d h ) v c o m d d v d h ( < + 6 . 0 v ) l v g l ( > - 1 5 . 0 v ) ( v g l - v c i ) v r e f s [ 3 : 0 ] ( x 1 . 4 7 ~ x 2 . 4 5 ) v c c ( 2 . 6 v ~ 3 . 3 v )
LG4572B ver. 1.0. 4 lge confidential 83 5.9.2 power on/off sequence 3 4 6 0 1 0 1 2 s l e e p d i s p l a y s l e e p f r a m e s l p ( 1 0 h , 1 1 h ) p f m v d l v c l v g l v g h r e s e t > 1 0 m s p o w e r s t a t e s l e e p _ i n 2 s l e e p _ o u t m e m o r y z z b 3 g a t e o n d i s p o n 4 5 0 1 2 1 b i a s o n r e g o n 0 1 5 0
LG4572B ver. 1.0. 4 lge confidential 84 5.9.3 display on sequence p o w e r s u p p l y ( v c c , i o v c c , v c i ) o n v c c i o v c c v c i 1 m s o r m o r e p o w e r o n r e s e t 1 0 m s o r m o r e r e g i s t e r s e t t i n g f o r d i s p l a y o n - i n v o f f o r i n v o n s e t t i n g - c o l m o d ( p i x e l d a t a f o r m a t s e t t i n g ) - i n t e r f a c e s e t t i n g - p a n e l c h a r a c t e r i s t i c s s e t t i n g - e n t r y m o d e s e t t i n g - d i s p l a y c o n t r o l 1 & 2 & 3 s e t t i n g - i n t e r n a l o s c i l l a t o r s e t t i n g - p o w e r c o n t r o l 3 , 4 , 5 , 6 s e t t i n g - c h a n n e l a m p o f f s e t c a n c e l i n g s e t t i n g - b a c k l i g h t c o n t r o l s e t t i n g - g a m m a s e t t i n g d i s p l a y o n s e q u e n c e s l p o u t ( 1 1 h ) 7 f r a m e s o r m o r e d i s p l a y o n
LG4572B ver. 1.0. 4 lge confidential 85 5.9.4 sleep in, out seq uence d i s p l a y o f f , s l e e p o n d i s p l a y o f f , s l e e p o n s e q u e n c e s l p i n ( 1 0 h ) 3 f r a m e s o r m o r e s l e e p o u t , d i s p l a y o n s l e e p o u t , d i s p l a y o n s e q u e n c e s l p o u t ( 1 1 h ) 7 f r a m e s o r m o r e d i s p l a y o n s l e e p i n , o u t s e q u e n c e
LG4572B ver. 1.0. 4 lge confidential 86 5.9.5 dstb in, dstb out , display on sequence d s t b i n , d s t b o u t , d i s p l a y o n s e q u e n c e s s l e e p m o d e d s t b i n s e q u e n c e p o w e r c o n t r o l 1 ( d s t b = 1 h ) 1 0 m s o r m o r e d s t b i n d s t b o u t s e q u e n c e c s = l o w c s = l o w 1 0 m s o r m o r e c s = l o w c s = l o w c s = l o w c s = l o w d s t b o u t v d d a l i v e v d d = 0 v v d d a l i v e d i s p l a y o n s e q u e n c e r e g i s t e r s e t t i n g f o r d i s p l a y o n s l e e p o u t ( 1 1 h ) d i s p l a y o n 7 f r a m e s o r m o r e
LG4572B ver. 1.0. 4 lge confidential 87 5.10 gamma correction function the lg 4572b has the gamma correction function to display in 16m colors simultaneously. the gamma correction is performed wi th 3 groups of registers determining eight reference grayscale levels, which are gradient adjustment, amplitude adjustment and fine - adjustment registers. each register groups further consists of register groups of positive and negative polarities. each reg ister group is set independently to other register groups, making the lg 4572b available with liquid crystal panels of various characteristics. figure 73 . grayscale control d b p i n r g b l c d d r i v e r l c d d r i v e r l c d d r i v e r l c d d i s p l a y d a t a b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 g 7 g 6 g 5 g 4 g 3 g 2 g 1 g 0 r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 b g r a y s c a l e g e n e r a t i o n g g r a y s c a l e g e n e r a t i o n r g r a y s c a l e g e n e r a t i o n g r a y s c a l e c o n t r o l < b > g r a y s c a l e c o n t r o l < g > g r a y s c a l e c o n t r o l < r >
LG4572B ver. 1.0. 4 lge confidential 88 5.10.1 grayscale generation unit con figuration the following figure illustrates the grayscale generation unit of the lg 4572b . to generate 64 grayscale voltages (v0 to v63), the lg 4572b first generates eight reference grayscale voltages (vinp0 - 7/vinn0 - 7). the grayscale generation unit then di vides eight reference grayscale voltages with the ladder resistors incorporated therein. figure 74 . grayscale generation unit f i n e a d j u s t m e n t ( 6 x 3 b i t s ) p k p / n 0 p k p / n 1 p k p / n 2 p k p / n 3 p k p / n 4 p k p / n 5 a m p l i t u d e a d j u s t m e n t v r p / n 0 v r p / n 1 8 t o 1 s e l e c t o r 8 t o 1 s e l e c t o r 8 t o 1 s e l e c t o r 8 t o 1 s e l e c t o r 8 t o 1 s e l e c t o r 8 t o 1 s e l e c t o r 3 3 3 3 3 3 3 3 5 5 g r a y - s c a l e o p - a m p v i n p 0 / v i n n 0 v i n p 1 / v i n n 1 v i n p 2 / v i n n 2 v i n p 3 / v i n n 3 v i n p 4 / v i n n 4 v i n p 5 / v i n n 5 v i n p 6 / v i n n 6 v i n p 7 / v i n n 7 v r e g 1 o u t , v r e g 2 o u t v g s , v g s _ n v 0 v 1 v 2 v 6 1 v 6 2 v 6 3 l a d d e r r e s i s t o r s p f p / n 1 p m p / n 0 p f p / n 2 p f p / n 3 3 3 3 3 3 i n c r e m e n t a d j u s t m e n t p r p / n 0 p r p / n 1 p f p / n 0
LG4572B ver. 1.0. 4 lge confidential 89 figure 75 . ladder re sistor units and 8 - to - 1 selectors 5.10.2 gamma correction register the gamma correction registers of the lg 4572b consist of gradient adjustment, amplitude adjustment, and fine adjustment registers, each of which has registers of positive and negative polarities. each v r e g 1 o u t 3 r ~ 2 4 r v r p 0 0 - 3 1 r 4 r * 7 8 t o 1 s e l 1 r * 7 8 t o 1 s e l v r h p 0 - 2 8 r 1 r * 7 8 t o 1 s e l 1 r * 7 8 t o 1 s e l 1 r * 7 8 t o 1 s e l v r l p 0 - 2 8 r 4 r * 7 8 t o 1 s e l v r p 1 0 - 3 1 r 8 r v g s v i n p 0 v i n p 1 v i n p 2 v i n p 3 v i n p 4 v i n p 5 v i n p 6 v i n p 7 3 r ~ 2 4 r 3 r ~ 2 4 r 3 r ~ 2 4 r 8 r ~ 6 4 r v r p 0 p f p 0 p r p 0 p f p 1 p m p p f p 2 p r p 2 p f p 3 v r p 1 3 r ~ 2 4 r v r n 0 0 - 3 1 r 4 r * 7 8 t o 1 s e l 1 r * 7 8 t o 1 s e l v r h n 0 - 2 8 r 1 r * 7 8 t o 1 s e l 1 r * 7 8 t o 1 s e l 1 r * 7 8 t o 1 s e l v r l n 0 - 2 8 r 4 r * 7 8 t o 1 s e l v r n 1 0 - 3 1 r 8 r v i n n 0 v i n n 1 v i n n 2 v i n n 3 v i n n 4 v i n n 5 v i n n 6 v i n n 7 3 r ~ 2 4 r 3 r ~ 2 4 r 3 r ~ 2 4 r 8 r ~ 6 4 r v r n 0 p f n 0 p r n 0 p f n 1 p m n p f n 2 p r n 2 p f n 3 v r n 1 v r 0 p v r 1 p v r 2 p v r 3 p v r m p v r 0 n v r 1 n v r 2 n v r m n v r 3 n p k p 0 p k p 1 p k p 2 p k p 3 p k p 4 p k p 5 p k n 0 p k n 1 p k n 2 p k n 3 p k n 4 p k n 5 v r e g 2 o u t v g s _ n
LG4572B ver. 1.0. 4 lge confidential 90 different register group can be set independently to others, enabling adjustment of grayscale voltage levels in relation to grayscales set optimally for gamma characteristics of a liquid crystal panel. these gamma correction register settings and the reference levels of the 64 grayscales to which the three kinds of adjustments are made (bold lines in the following figure) are common to all rgb dots. figure 76 . gamma adjustments gradient adjustment registers the gradient adjustment registers are used to adjust the gradient of the curve representing the relationship between the grayscale and the grayscale voltage level around middle grayscales without changing the dynamic range. to adjust the gradient , the resistance values of grayscale reference voltage generating variable resistors (vrhp(n)/vrlp(n)) in the middle of the ladder resistor unit are adjusted. the registers consist of positive and negative polarity registers, allowing asymmetric drive. amp litude adjustment registers the amplitude adjustment registers are used to adjust the amplitude of grayscale voltages. to adjust the amplitude, the resistance values of the grayscale voltage generating variable resistors (vrp(n)1/0) at the top and bottom o f the ladder resistor unit are adjusted. same with the gradient registers, the amplitude adjustment registers consist of positive and negative polarity registers. fine adjustment registers the fine adjustment registers are used to fine - adjust grayscale vol tage levels. to fine - adjust grayscale voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels for each register generated from the ladder resistor unit, in respective 8 - to - 1 selectors. same with other registers, the fine adj ustment registers consist of positive and negative polarity registers. table 10 . list of registers register groups positive polarity negative polarity description gradient adjustment prp0[2:0] prn0[2:0] variable resistor vrhp(n) prp1[2:0] prn1[2:0] variable resistor vrhp(n) pfp0[2:0] pfn0[2:0] variable resistor vr0p(n) pfp1[2:0] pfn1[2:0] variable resistor vr1p(n) pfp2[2:0] pfn2[2:0] variable resistor vr2p(n) pfp3[2:0] pfn3[2:0] variable resistor vr3p(n) pmp[2:0] pmn [2:0] variable resistor vrmp(n) amplitude adjustment vrp0[4:0] vrn0[4:0] variable resistor vrp(n)0 vrp1[4:0] vrn1[4:0] variable resistor vrp(n)1 fine adjustment pkp0[2:0] pkn0[2:0] 8 - to - 1 selector ( voltage level of grayscale 1) pkp1[2:0] pkn1[2:0 ] 8 - to - 1 selector ( voltage level of grayscale 8) pkp2[2:0] pkn2[2:0] 8 - to - 1 selector ( voltage level of grayscale 20) g r a y s c a l e n u m b e r g r a y s c a l e v o l t a g e g r a d i e n t a d j u s t m e n t g r a y s c a l e n u m b e r g r a y s c a l e v o l t a g e a m p l i t u d e a d j u s t m e n t g r a y s c a l e n u m b e r g r a y s c a l e v o l t a g e f i n e a d j u s t m e n t
LG4572B ver. 1.0. 4 lge confidential 91 pkp3[2:0] pkn3[2:0] 8 - to - 1 selector ( voltage level of grayscale 43) pkp4[2:0] pkn4[2:0] 8 - to - 1 selector ( voltage level of graysca le 53) pkp5[2:0] pkn5[2:0] 8 - to - 1 selector ( voltage level of grayscale 62) 5.10.3 ladder resistors and 8 - to - 1 selector block configuration the grayscale generation unit as illustrated in figure 75 consists of two la dder resistor units including variable resistors and 8 - to - 1 selectors. each 8 - to - 1 selector selects one of the 8 voltage levels generated from the ladder resistor unit to output as a grayscale reference voltage. both variable resistors and 8 - to - 1 selectors are controlled according to the gamma correction registers. this unit has pins to connect a volume resistor externally to compensate differences in various characteristics of panels. variable resistors the lg 4572b uses variable resistors of the following three purposes: gradient adjustment (vrhp(n)/vrlp(n)/vr0~4p(n)/vrmp(n)) and amplitude adjustment (vrp(n)0~1). the resistance values of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as follows. table 11 . amplitude adjustment contents of register vrp(n)0[4:0] resistance vrp(n)0 vrp(n)1 00000 0r 00001 1r 00010 2r : : : : 11101 29r 11110 30r 11111 31r 8 - to - 1 selectors the 8 - to - 1 selector selects one of eight voltage levels g enerated from the ladder resistor unit according to the fine adjustment register, and output the selected voltage level as a reference grayscale voltage (vinp(n)1~ vinp(n 6). the table below shows the setting in the fine adjustment register and the selecte d voltage levels for respective reference grayscale voltages . table 12 . fine adjustment registers and selected voltage pkp(n)[2:0] selected voltage vinp(n)1 vinp(n)2 vinp(n)3 vinp(n)4 vinp(n)5 vinp(n)6 3?h0 kvp(n)1 kvp(n)9 kvp(n )17 kvp(n)25 kvp(n)33 kvp(n)41 3?h1 kvp(n)2 kvp(n)10 kvp(n)18 kvp(n)26 kvp(n)34 kvp(n)42 3?h2 kvp(n)3 kvp(n)11 kvp(n)19 kvp(n)27 kvp(n)35 kvp(n)43 3?h3 kvp(n)4 kvp(n)12 kvp(n)20 kvp(n)28 kvp(n)36 kvp(n)44 3?h4 kvp(n)5 kvp(n)13 kvp(n)21 kvp(n)29 kvp(n)3 7 kvp(n)45 3?h5 kvp(n)6 kvp(n)14 kvp(n)22 kvp(n)30 kvp(n)38 kvp(n)46 3?h6 kvp(n)7 kvp(n)15 kvp(n)23 kvp(n)31 kvp(n)39 kvp(n)47 3?h7 kvp(n)8 kvp(n)16 kvp(n)24 kvp(n)32 kvp(n)40 kvp(n)48
LG4572B ver. 1.0. 4 lge confidential 92 the grayscale voltage levels for v0~v63 grayscales are calculated from the following formula. table 13 . formula for calculating voltage (1) pin formula fine adjustment register value reference voltage kvp0 vreg1out - ? v x vrp0/sumrp - vinp0 kvp1 vreg1out - ? v x (vrp0+vr0p+0r)/sumrp pkp0= 3?h0 vinp1 kvp2 vreg1out - ? v x (vrp0+vr0p+4r)/sumrp pkp0= 3?h1 kvp3 vreg1out - ? v x (vrp0+vr0p+8r)/sumrp pkp0= 3?h2 kvp4 vreg1out - ? v x (vrp0+vr0p+12r)/sumrp pkp0= 3?h3 kvp5 vreg1out - ? v x (vrp0+vr0p+16r)/sumrp pkp0= 3?h4 kvp6 vreg1out - ? v x (vrp0 +vr0p+20r)/sumrp pkp0= 3?h5 kvp7 vreg1out - ? v x (vrp0+vr0p+24r)/sumrp pkp0= 3?h6 kvp8 vreg1out - ? v x (vrp0+vr0p+28r)/sumrp pkp0= 3?h7 kvp9 vreg1out - ? v x (vrp0+vr0p+28r+vrhp)/sumrp pkp1= 3?h0 vinp2 kvp10 vreg1out - ? v x (vrp0+vr0p+29r+vrhp)/sumrp pkp1= 3?h1 kvp11 vreg1out - ? v x (vrp0+vr0p+30r+vrhp)/sumrp pkp1= 3?h2 kvp12 vreg1out - ? v x (vrp0+vr0p+31r+vrhp)/sumrp pkp1= 3?h3 kvp13 vreg1out - ? v x (vrp0+vr0p+32r+vrhp)/sumrp pkp1= 3?h4 kvp14 vreg1out - ? v x (vrp0+vr0p+33r+vrhp)/sumrp pkp1= 3 ?h5 kvp15 vreg1out - ? v x (vrp0+vr0p+34r+vrhp)/sumrp pkp1= 3?h6 kvp16 vreg1out - ? v x (vrp0+vr0p+35r+vrhp)/sumrp pkp1= 3?h7 kvp17 vreg1out - ? v x (vrp0+vr0/1p+35r+vrhp)/sumrp pkp2= 3?h0 vinp3 kvp18 vreg1out - ? v x (vrp0+vr0/1p+36r+vrhp)/sumrp pkp2= 3?h1 kvp19 vreg1out - ? v x (vrp0+vr0/1p+37r+vrhp)/sumrp pkp2= 3?h2 kvp20 vreg1out - ? v x (vrp0+vr0/1p+38r+vrhp)/sumrp pkp2= 3?h3 kvp21 vreg1out - ? v x (vrp0+vr0/1p+39r+vrhp)/sumrp pkp2= 3?h4 kvp22 vreg1out - ? v x (vrp0+vr0/1p+40r+vrhp)/sumrp pkp2= 3?h5 kvp23 vreg1out - ? v x (vrp0+vr0/1p+41r+vrhp)/sumrp pkp2= 3?h6 kvp24 vreg1out - ? v x (vrp0+vr0/1p+42r+vrhp)/sumrp pkp2= 3?h7 kvp25 vreg1out - ? v x (vrp0+vr0/1p+42r+vrhp +vrmp)/sumrp pkp3= 3?h0 vinp4 kvp26 vreg1out - ? v x (vrp0+vr0/1p+43r+vrhp +v rmp)/sumrp pkp3= 3?h1 kvp27 vreg1out - ? v x (vrp0+vr0/1p+44r+vrhp +vrmp)/sumrp pkp3= 3?h2 kvp28 vreg1out - ? v x (vrp0+vr0/1p+45r+vrhp +vrmp)/sumrp pkp3= 3?h3 kvp29 vreg1out - ? v x (vrp0+vr0/1p+46r+vrhp +vrmp)/sumrp pkp3= 3?h4 kvp30 vreg1out - ? v x (vrp0+vr0/1p+47r+vrhp +vrmp)/sumrp pkp3= 3?h5 kvp31 vreg1out - ? v x (vrp0+vr0/1p+48r+vrhp +vrmp)/sumrp pkp3= 3?h6 kvp32 vreg1out - ? v x (vrp0+vr0/1p+49r+vrhp +vrmp)/sumrp pkp3= 3?h7 kvp33 vreg1out - ? v x (vrp0+vr0/1/2p+49r+vrhp +vrmp)/sumrp pkp4= 3?h 0 vinp5 kvp34 vreg1out - ? v x (vrp0+vr0/1/2p+50r+vrhp +vrmp)/sumrp pkp4= 3?h1 kvp35 vreg1out - ? v x (vrp0+vr0/1/2p+51r+vrhp +vrmp)/sumrp pkp4= 3?h2 kvp36 vreg1out - ? v x (vrp0+vr0/1/2p+52r+vrhp +vrmp)/sumrp pkp4= 3?h3 kvp37 vreg1out - ? v x (vrp0+vr0 /1/2p+53r+vrhp +vrmp)/sumrp pkp4= 3?h4 kvp38 vreg1out - ? v x (vrp0+vr0/1/2p+54+vrhp +vrmp)/sumrp pkp4= 3?h5 kvp39 vreg1out - ? v x (vrp0+vr0/1/2p+55r+vrhp +vrmp)/sumrp pkp4= 3?h6 kvp40 vreg1out - ? v x (vrp0+vr0/1/2p+56r+vrhp +vrmp)/sumrp pkp4= 3?h7
LG4572B ver. 1.0. 4 lge confidential 93 pin formula fine adjustment register value reference voltage kvp41 vreg1out - ? v x (vrp0+vr0/1/2p+56r+vrhp +vrmp+vrlp)/sumrp pkp5= 3?h0 vinp6 kvp42 vreg1out - ? v x (vrp0+vr0/1/2p+60r+vrhp +vrmp+vrlp)/sumrp pkp5= 3?h1 kvp43 vreg1out - ? v x (vrp0+vr0/1/2p+64r+vrhp +vrmp+vrlp)/sumrp pkp5= 3?h2 kvp44 vreg1out - ? v x (vrp0+vr0/1/2p+68r+vrhp +vrmp+vrlp)/sumrp pkp5= 3?h3 kvp45 vreg1out - ? v x (vrp0+vr0/1/2p+72r+vrhp +vrmp+vrlp)/sumrp pkp5= 3?h4 kvp46 vreg1out - ? v x (vrp0+vr0/1/2p+76r+vrhp+vrmp +vrlp)/sumrp pkp5= 3?h5 kvp47 vreg1out - ? v x (vrp0+vr0/1/2p+80r+vrhp +vrmp +vrlp)/sumrp pkp5= 3?h6 kvp48 vreg1out - ? v x (vrp0+vr0/1/2p+84r+vrhp+vrmp +vrlp)/sumrp pkp5= 3?h7 kvp49 vreg1out - ? v x (vrp0+vr0/1/2/3p+84r+vrhp+vrmp +vrlp)/sumrp - vinp7 sumrp: sum of positive ladder resistors = 92r+vrhp+vrlp+vrp0+vrp1+vr0p+v r1p+vr2p+vr3p+vrmp ? v: difference in electrical potential between vreg1out and vgs
LG4572B ver. 1.0. 4 lge confidential 94 table 14 . formula for calculating voltage (2) grayscale voltage formula v0 vinp0 v1 vinp1 v2 vinp2+(vinp1 - vinp2) x (30/48) v3 vinp2+(vinp1 - vin p2) x (23/48) v4 vinp2+(vinp1 - vinp2) x (16/48) v5 vinp2+(vinp1 - vinp2) x (12/48) v6 vinp2+(vinp1 - vinp2) x (8/48) v7 vinp2+(vinp1 - vinp2) x (4/48) v8 vinp2 v9 vinp3+(vinp2 - vinp3) x (22/24) v10 vinp3+(vinp2 - vinp3) x (20/24) v11 vinp3+(vinp2 - vinp3) x (1 8/24) v12 vinp3+(vinp2 - vinp3) x (16/24) v13 vinp3+(vinp2 - vinp3) x (14/24) v14 vinp3+(vinp2 - vinp3) x (12/24) v15 vinp3+(vinp2 - vinp3) x (10/24) v16 vinp3+(vinp2 - vinp3) x (8/24) v17 vinp3+(vinp2 - vinp3) x (6/24) v18 vinp3+(vinp2 - vinp3) x (4/24) v19 vin p3+(vinp2 - vinp3) x (2/24) v20 vinp3 v21 vinp4+(vinp3 - vinp4) x (22/23) v22 vinp4+(vinp3 - vinp4) x (21/23) v23 vinp4+(vinp3 - vinp4) x (20/23) v24 vinp4+(vinp3 - vinp4) x (19/23) v25 vinp4+(vinp3 - vinp4) x (18/23) v26 vinp4+(vinp3 - vinp4) x (17/23) v27 vinp 4+(vinp3 - vinp4) x (16/23) v28 vinp4+(vinp3 - vinp4) x (15/23) v29 vinp4+(vinp3 - vinp4) x (14/23) v30 vinp4+(vinp3 - vinp4) x (13/23) v31 vinp4+(vinp3 - vinp4) x (12/23) grayscale voltage formula v32 vinp4+(vinp3 - vinp4) x (11/23) v33 vinp4+(vinp3 - vinp4) x (10/23) v34 vinp4+(vinp3 - vi np4) x (9/23) v35 vinp4+(vinp3 - vinp4) x (8/23) v36 vinp4+(vinp3 - vinp4) x (7/23) v37 vinp4+(vinp3 - vinp4) x (6/23) v38 vinp4+(vinp3 - vinp4) x (5/23) v39 vinp4+(vinp3 - vinp4) x (4/23) v40 vinp4+(vinp3 - vinp4) x (3/23) v41 vinp4+(vinp3 - vinp4) x (2/23) v42 vinp4+(vinp3 - vinp4) x (1/23) v43 vinp4 v44 vinp5+(vinp4 - vinp5) x (22/24) v45 vinp5+(vinp4 - vinp5) x (20/24) v46 vinp5+(vinp4 - vinp5) x (18/24) v47 vinp5+(vinp4 - vinp5) x (16/24) v48 vinp5+(vinp4 - vinp5) x (14/24) v49 vinp5+(vinp4 - vinp5) x (12/24) v50 vinp5+(vinp4 - vinp5) x (10/24) v51 vinp5+(vinp4 - vinp5) x (8/24) v52 vinp5+(vinp4 - vinp5) x (6/24) v53 vinp5+(vinp4 - vinp5) x (4/24) v54 vinp5+(vinp4 - vinp5) x (2/24) v55 vinp5 v56 vinp6+(vinp5 - vinp6) x (44/48) v57 vinp6+(vinp5 - vinp6) x (40/48) v58 vinp 6+(vinp5 - vinp6) x (36/48) v59 vinp6+(vinp5 - vinp6) x (32/48) v60 vinp6+(vinp5 - vinp6) x (25/48) v61 vinp6+(vinp5 - vinp6) x (18/48) v62 vinp6 v63 vinp7 note s : 1. make sure ddvdh - v0 > 0.5v 2. based on the generated 64 gray levels above, interpolated 4 levels are newly generated. eventually total 253 gray levels are generated to acquire 16.2m color depth.
LG4572B ver. 1.0. 4 lge confidential 95 5.11 oscillator lg 4572b could generate rc oscillation with an internal oscillation resistor and capacitor for the main display clock and power boosting circuit, li ke as step - up and step - down.
LG4572B ver. 1.0. 4 lge confidential 96 5.12 otp control lg 4572b has an embedded otp which is a 32 - bit one - time programmable (otp) ip from ememory technology inc. ( eo01x32 bdv 6 ). eo01x32bdv6 is a cmos, 1bit (1 - bit) program otp logic device. the main memory block is orga nized as 8 - bits by 4 banks. see the data sheet of eo01x32bdv6 . the pins of the embedded otp can be controlled using the otp control 1 (c4h) register as shown below. table 15 . otp setting conditions eo01x32bdv6 bit fields of registe r c4h ptm = 0v/ vdd ptm[1:0] = 00/11 prd = 0v/ vdd prd = 0/1 vpp = vdd / 7.75v vpp = 0/1 pprog = 0v/ vdd pprog = 0/1 pwe = 0v/ vdd pwe = 0/1 pa[1:0] = 0v/ vdd pa[1:0] = 0/1 pdin[7:0] = 0v/ vdd pdin[7:0] = 0/1 the ra[1:0] of register f9h selects one of fou r otp bytes. accessing otp control registers, follow the timing requirements of read and program cycles.
LG4572B ver. 1.0. 4 lge confidential 97 figure 77 . otp timing table 16 . otp timing characteristics parameter sym bol eo01x32bdv6 unit min max rising time / falling time tr / tf - 1 ns data access time taa - 70 ns power - on pulse width time t prd 200 - ns address / data setup time tas / tds 4 - ns address / data hold time tah / tdh 9 - ns external vpp setup ti me tvps 0 - ns external vpp hold time tvph 0 - ns program recovery time tvr 10 - s program pulse width tpw 300 350 s vdd setup time tvds 0 - ms vdd recovery time tvdr 0 - ms pprog setup time tpps 10 - ns pprog recovery time tppr 10 - ns power on read time trst 20 - ns notes : r e a d c y c l e v d d v p p p r d p d o b [ 3 1 : 0 ] t v d s t r s t t p o r t a a t v d r 0 v 1 . 5 v 0 v 1 . 5 v 0 v 0 v x x x d a t a o u t x x x p r o g r a m c y c l e t v d s t v p s t p p s t v d r t p p r t v p h t p w t a s t a h t v r t d s t d h v a l i d a d d r . v a l i d a d d r . v a l i d d a t a v a l i d d a t a x x x x x x x x x x x x n e x t o p e r a t i o n 1 . 5 v 7 . 7 5 v 1 . 5 v 1 . 5 v 0 v 0 v 0 v 0 v v d d v p p p p r o g p w e p a [ 1 : 0 ] p d i n [ 7 : 0 ]
LG4572B ver. 1.0. 4 lge confidential 98 1. all electrical and timing parameters listed above are based on spice (or equivalent) simulations and subject to changes after silicon verification. 2. all program signals that align together in the timing diagrams should be der ived from the rising clock edge. 3. all timing measurements are from the 50% of the input to 50% of the output. 4. all input waveforms have rising time (tr) and falling time (tf) of 1ns from 10% to 90% of the input waveforms. 5. for capacitive loads greater than 1p f, access time will increase by 1ns per pf of additional loading. 6. program time means one byte program time in user mode the following sequences are for writing and reading data into and/or from otp .
LG4572B ver. 1.0. 4 lge confidential 99 figure 78 . otp programming sequence o t p p r o g r a m m i n g s e q u e n c e o t p w r i t e s e t t i n g 1 f 8 h : p r d = 0 , v p p = 0 , p p r o g = 1 , p w e = 0 , p d i n = 8 ' h x x o t p w r i t e s e t t i n g 2 f 8 h : p r d = 0 , v p p = 1 , p p r o g = 1 , p w e = 0 , p d i n = 8 ' h x x o t p w r i t e s e t t i n g 3 f 8 h : p r d = 0 , v p p = 1 , p p r o g = 1 , p w e = 0 , p d i n [ 7 ] = 0 , p d i n [ 6 : 0 ] = 7 ' h 0 0 - 7 f o t p w r i t e s e t t i n g 5 f 8 h : p r d = 0 , v p p = 1 , p p r o g = 1 , p w e = 0 , p d i n [ 7 ] = 0 , p d i n [ 6 : 0 ] = 7 ' h 0 0 - 7 f o t p w r i t e s e t t i n g 6 f 8 h : p r d = 0 , v p p = 0 , p p r o g = 1 , p w e = 0 , p d i n = 8 ' h x x o t p w r i t e s e t t i n g 7 f 8 h : p r d = 0 , v p p = 0 , p p r o g = 0 , p w e = 0 , p d i n = 8 ' h x x o t p s e t t i n g v e r i f i c a t i o n 1 f 8 h : p r d = 1 , v p p = 0 , p p r o g = 0 , p w e = 0 , p d i n = 8 ' h x x o t p s e t t i n g v e r i f i c a t i o n 2 f 8 h : p r d = 0 , v p p = 0 , p p r o g = 0 , p w e = 0 , p d i n = 8 ' h x x p o w e r s u p p l y o n ( v p p 1 ) 1 0 m s o r m o r e 1 m s o r m o r e 1 0 u s o r m o r e o t p a d d r e s s s e t t i n g 1 f 8 h : p r d = 1 , v p p = 0 , p p r o g = 0 , p w e = 0 , p d i n = 8 ' h x x o t p a d d r e s s s e t t i n g 2 f 8 h : p r d = 0 , v p p = 0 , p p r o g = 0 , p w e = 0 , p d i n = 8 ' h x x o t p w r i t e d a t a i n a n o t h e r a d d r e s s ? p o w e r s u p p l y o f f ( v p p 1 ) n o y e s 3 0 0 u s ~ 3 5 0 u s o t p w r i t e s e t t i n g 4 f 8 h : p r d = 0 , v p p = 1 , p p r o g = 1 , p w e = 1 , p d i n [ 7 ] = 0 , p d i n [ 6 : 0 ] = 7 ' h 0 0 - 7 f g n d v p p = 7 . 5 v g n d v p p = 7 . 5 v p o w e r s u p p l y o n ( v c c , v c i , i o v c c ) v c c g n d v c c i o v c c v c i 1 m s o r m o r e
LG4572B ver. 1.0. 4 lge confidential 100 figure 79 . otp read sequence o t p r e a d s e q u e n c e p o w e r s u p p l y o n ( v c c , v c i , i o v c c ) v c c g n d v c c i o v c c v c i o t p l o a d f 8 h : p r d = 1 o t p l o a d e n d f 8 h : p r d = 0 o t p d a t a r e a d o u t f a h : i n s t r u c t i o n r e a d
LG4572B ver. 1.0. 4 lge confidential 101 5.13 eeprom control if there is an external eeprom connected to lg 4572b , lg 4572b can do register writing through eeprom reading function via i2c interface. only data reading from eeprom is available in lg 4572b . data writing to eeprom device from lg 4572b is not supported. after sleep out, rom data reading operation will start according to the following format. only if this format of data written in eeprom can be read into lg 4572b , which means register writing. { length, address, data } for example, if user wants to do register writing of bgammap and bgamman in the manufacture command set, the rom data should be written as following pat tern. figure 80 . one example of eeprom data format to be read by lg 4572b there are two pads in lg 4572b for i2c interface. t h ey are rsda and rscl. the rsda is for reading data from eeprom. this pad sh ould be connected to external pull - up resistor with around 10kohm. and the other node of this pull - up resistor 10kohm is connected to iovcc. the application is as follows. 0 9 d 4 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 9 d 5 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 l e n g t h a d d r . d a t a l e n g t h a d d r . d a t a e n d i n g i o v c c l g 4 5 7 2 r s d a 1 0 k o h m e e p r o m
LG4572B ver. 1.0. 4 lge confidential 102 figure 81 . connection diagr am of eeprom and lg 4572b with 10kohm external resistor between rsda and iovcc. the rscl is a clock for data reading from eerpom and is an output signal. the maximum frequency of rscl should be less than 400khz. to set the frequency of rscl, the following equation can be used. rscl frequency = (rc osc frequency ) / (16 C rfclk) where the rfclk can be set from 0 to 12 using rfclk[3:0] register. the other values of 13, 14, and 15 are not valid. the frequency of rc osc can be set by using frs[4:0] register . the following is for easy reading data from external eeprom. the maximum rscl frequency can limit the number of writable registers in lg 4572b . because the wait time in the following eeprom read operation diagram is less than 5ms normally. but the system a llows the longer wait time, the number of writable registers in lg 4572b can be increased. figure 82 . eerpom read operation by lg 4572b r e g i s t e r s e t t i n g f o r e e r p o m r e a d i n g f u n c t i o n - e e p r o m = 1 h - f r s [ 4 : 0 ] = 1 0 h - r f c l k [ 3 : 0 ] = 0 a h s l e e p o u t s t a r t e e p r o m r e a d w a i t 5 m s e n d e e r p o m r e a d e e p r o m r e a d o p e r a t i o n
LG4572B ver. 1.0. 4 lge confidential 103 6 command s 6.1 command list user command set name addr size r/ n w d/ n c b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 default description nop 00h 0 w 0 no operation swreset 01h 0 w 0 swrst = 1 (self cleared after a fixed delay) 0 software reset rddpm 0ah 1 r 0 read display power mode 1 0 idm ptl nslp nor disp 0 0 08h rddmadctl 0bh 1 r 0 read display madctl 1 my mx mv 0 bgr 0 fh fv 00h rddcolmod 0ch 1 r 0 read display pixel format 1 0 dpipf[2:0] 0 dbipf[2:0] 77h rddim 0dh 1 r 0 read display image mode 1 0 0 inv 0 0 0 0 0 00h rddsm 0eh 1 r 0 read display si gnal mode 1 te tem 00h slpin 10h 0 w 0 nslp = 1 0 sleep in powers for the display are off slpout 11h 0 w 0 nslp = 0 sleep out powers for the display are on ptlon 12h 0 w 0 ptl = 1 0 partial mode on nrton 13h 0 w 0 nor = 1 (equivalently ptl = 0 and vscr = 0) 1 normal display mode on invoff 20h 0 w 0 inv = 0 0 display inversion off invon 21h 0 w 0 inv = 1 display inversion on dispoff 28h 0 w 0 disp = 0 0 display off dispon 29h 0 w 0 disp = 1 display on caset 2ah 4 w 0 set column addr ess 1 sc[9:8] 00h sc C start column address ec C end column address 1 sc[7:0] 00h 1 ec[9:8] 01h 1 ec[7:0] dfh paset 2bh 4 w 0 set page address 1 sp[9:8] 00h sp C start page address ep C end page address 1 sp[7:0] 00h 1 ep[9:8] 03h 1 ep[7:0] 5fh ramwr 2ch variable w 0 db[23:0] write memory start ramrd 2eh variable r 0 db[23:0] read memory start ptlar 30h 4 w 0 partial area definition 1 sr[9:8] 00h sr C start row er C e nd row 1 sr[7:0] 00h 1 er[9:8] 03h 1 er[7:0] 5fh teoff 34h 0 w 0 te = 0 00h tearing effect line off teon 35h 1 w 0 te = 1 tearing effect line on 1 tem 00h tem - mode of the te output line madctl 36h 1 w 0 memory ac cess control
LG4572B ver. 1.0. 4 lge confidential 104 1 my mx mv bgr fh fv 00h my C page address order mx C column address order mv C page/column addressing order bgr C rgb/bgr order fh C flip horizontal (=dir) fv C flip vertical (=gs) idmoff 38h 0 w 0 idm = 0 idle mode off full color de pth is used on the display panel. idmon 39h 0 w 0 idm = 1 idle mode on reduced color depth is used on the display panel. colmod 3ah 1 w 0 interface pixel format 1 dpipf[2:0] dbipf[2:0] 77h dpipf[2:0] - dpi pixel format dpipf[2:0] - dbi pixel fo rmat ramwrc 3ch variable w 0 db[23:0] write memory continue ramrdc 3eh variable r 0 db[23:0] read memory continue te line 44h 2 w 0 set tear scanline 1 teline[ 15 :8] 00h teline - tear scanline 1 teline [7:0] 00h scanline 45h 2 r 0 get sc anline 1 scanline[ 15 : 8 ] xxh scanline C read display scanline 1 scanline [7:0] xxh wrdisbv 51h 1 w 0 write display brightness 1 dbv [7:0] 00h dbv - manual display brightness rddisbv 52h 1 r 0 read display brightness value 1 dbv [ 7:0] 00h wrctrld 53h 1 w 0 write control display 1 bctrl dd bl 00h bctrl C brightness control block on/off dd C display dimming for manual brightness setting bl C backlight control on/off rdctrld 54h 1 r 0 read control display 1 bct rl dd bl xxh wrcabc 55h 1 w 0 write content adaptive brightness control 1 cabc[1:0] 00h cabc - content adaptive brightness control mode rdcabc 56h 1 r 0 read content adaptive brightness control 1 cabc[1:0] 00 h wrcabcmb 5eh 1 w 0 write cabc minimum brightness 1 cmb[7:0] 00h cmb - minimum brightness rdcabcmb 5fh 1 r 0 read cabc minimum brightness 1 cmb[7:0] 00 h rdddb a1h variable r 0 read ddb start 1 db[23:0] - rdddbc a8h variable r 0 read ddb cont inue 1 db[23:0] -
LG4572B ver. 1.0. 4 lge confidential 105 manufactu rer command set name addr size r/nw d/ nc b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 default description rgbif b1 3 r/w 0 rgb interface setting 1 dpicc sync ckpl hspl vspl depl 06h dpicc - dpi color coding (see table 6 ) 0: con fig 1 for both 16bpp and 18bpp, 1: config 3 for 16bpp and config 2 for 18bpp sync C sync mode, 0: vs+hs+de , 1: vs+hs ckpl C pclk polarity. rising(0) or falling (1) edge. hspl C hsync polarity. active high(0) or low(1) vspl C vsync polarity. active hig h(0) or low(1) depl C de polarity. active high(0) or low(1) 1 hbp[6:0] 1eh hbp C h back porch in pclk ( used only if rgbif , sync = 1 ) 1 vbp[7:0] 0ch vbp C v back porch in line ( used only if rgbif , sync = 1 ) panelset b2h 2 r/w 0 panel cha racteristics setting 1 lr selp hrs[1:0] rev 10h hrs C h resolution. 0: 480 pixels, 1: 360 pixels, 2: 320, 3:240 rev C normally black (0) or white (1) panel selp C panel 1: hydis 0 : lgd lr C gate l/r signal control 1 vrs[7:0] d8h vrs C v resol ution divided by 4(nl) paneldrv b3h 1 r/w 0 panel drive setting 1 dinv[1:0] 02h dinv C dot inversion mode 0: column inversion, 1: 1 - dot, 2: 2 - dot, 3: 3 - dot dispmode b4h 1 r/w 0 display mode control 1 dith 04h dith C dither enab le (1:enable, 0:truncation) dispctl1 b5 5 r/w 0 display control 1 (source output control) 1 sdt[7:0] 10h sdt C source output delay; [1:255] pixel clocks 1 shpn[6:0] 10h shpn C equalize level period; [0.. 127 ] pixel clocks 1 engnd[6:0] 10 h engnd C gnd level period; [1.. 127 ] pixel clocks 1 shiz[7:0] 00h shiz C source output hi - z control via sap 1 pts[1:0] slt 2 0h pts C source output in non - display area 0 : black, 10 : gnd, 11 : high - z slt C spread source output s dispctl2 b6 h 6 r/w 0 display control 2 (gate output control) 1 gswap fvst asg sdm fhn 01h gswap C 1: enable gclk swap, 0:normal gclk fvst C 1 : 2 - phase advanced, 0:normal phase asg C 1: single drive, 0: dual drive fhn C 1: overlap, 0: non overlap sdm C 1: 8 phases, 0: 4 phases 1 clw[7:0] 18h clw C gclk non - overlap timing; [1.. 255 ] pixel clocks 1 gto[5:0] 02h gto C gpwr toggle frequency; [1..63] frames 1 gno[7:0] 40h gno C gpwr non - overlap timing; [1.. 255 ] pixel clocks 1 fti[7:0] 10h ft i C gvst output delay; [1.. 255] pixel clocks 1 gpm[7:0] 00h gpm C d uration of gate pulse modulation dispctl3 b7h 5 r/w 0 display control 3 (command mode display)
LG4572B ver. 1.0. 4 lge confidential 106 1 rtn[7:0] 46h rtn C sets 1h(line) period. [70~255] 1 fp[7:0] 06h fp - verti cal front porch of command mode display 1 bp[7:0] 0ch bp - vertical back porch of command mode display 1 div[1:0] 00h div - division ratio of the internal oscillator 1 tei[2:0] 00h tei - te output interval in frames oscset c0h 2 r/w 0 internal oscillator setting 1 osc sync ext osc osc 01h oscsync C osc sync mode control extosc C use the external osc instead of internal osc osc C use the internal osc instead of pclk for step - up circuits 1 frs[4:0] 00h frs C osc illator frequency control pwrctl1 c1h 1 r/w 0 power control 1 (power state selection) 1 dte stb dstb 02h dte C manual gate output enable dstb C deep standby mode stb C standby bias state disable pwrctl2 c2h 1 r/w 0 power control 2 (manual s tep - up circuit enable) 1 lvgl vdl vcl vgl vgh vdh 00h lvgl - enable step - up circuit for lvgl vdl - enable step - up circuit for vdl vcl - enable step - up circuit for vcl (= vcomg) vgl - enable step - up circuit for vgl (= pon) vgh - enable step - up circui t for vgh vdh - enable pfm boost circuit for ddvdh pwrctl3 c3h 5 r/w 0 power control 3 (step - up circuit control) 1 stmode[2:0] 00h step - up auto power mode 1 dc1[2:0] 04h frequency of the step - up circuit 2 1 dc2[2:0] 03h fre quency of the step - up circuit 3 1 dc3[2:0] 03h frequency of the step - up circuit 4 1 dcpfm[2:0] 04h frequency of the pfm boost circuit pwrctl4 c4h 6 r/w 0 power control 4 (regulator control) 1 opb bmb bdc[2:0] 00h opb C normal & buffered bias selection bmb C bias line current adjustment bdc C channel amp bias current control 1 gdc[2:0] ap[2:0] 00h gdc C gray C scale amp bias current control ap C a djusts the constant current in the operational amplifier circuit in the lcd power supply circuit. 1 vrh1[4:0] 00h vreg1out level control 1 vrh2[4:0] 00h vreg 2 out level control 1 reg pd bt[2:0] 05h regpd C regulator power down bt C vgh/vgl level control 1 vbs[2:0] vref[3:0] 0bh vbs C set the vbias le vel. vref C set the reference voltage of ddvdh. pwrctl5 c5h 1 r/w 0 power control 5 (vcom control) 1 vcm[6:0] 00h vcm C vcom level control pwrctl6 c6h 3 r/w 0 power control 6 (vdd regulator control)
LG4572B ver. 1.0. 4 lge confidential 107 1 ri[2:0] rv[2:0] 23h ri C vdd current control rv C vdd voltage control 1 rset[2:0] rcont[2:0] 40h rcont C main bias voltage control rset C main bias current control ofcctl c7h 3 r/w 0 source channel amp offset cancelling control 1 ofcen 00h ofcen C offset canceling enabl e 1 ofctsw[7:0] 30h ofctsw C offset sampling time control [1..255] 1 ofctd2[3:0] ofctd1[3:0] 10h ofctd1 C offset sampling time delay [0..15] ofctd2 C offset canceling time delay [0..15] blctl c8h 2 r/w 0 backlight control 1 cdsp[3:0] cdmp [3:0] 82h cdsp C dimming control of still picture cdmp C dimming control of moving picture 1 pwmp fpwm[1:0] 01h pwmp - pwm polarity. 0: active h, 1: active l fpwm - pwm frequency setting rgammap d0h 9 r/w 0 set positive gamma curve for red 1 pkp1[2:0] pkp0[2:0] 00h 1 pkp3[2:0] pkp2[2:0] 00h 1 pkp5[2:0] pkp4[2:0] 00h 1 prp1[2:0] prp0[2:0] 00h 1 vrp0[4:0] 00h 1 vrp1[4:0] 00h 1 pfp1[2:0] pfp0[2:0] 00h 1 pfp3[2:0] pfp2[2:0] 00h 1 pmp[2:0] 00h rgamman d1h 9 r/w 0 set negative gamma curve for red 1 pkn1[2:0] pkn0[2:0] 00h 1 pkn3[2:0] pkn2[2:0] 00h 1 pkn5[2:0] pkn4[2:0] 00h 1 prn1[2:0] prn0[2:0] 00h 1 vrn0[4:0] 00h 1 vrn1[4:0 ] 00h 1 pfn1[2:0] pfn0[2:0] 00h 1 pfn3[2:0] pfn2[2:0] 00h 1 pmn[2:0] 00h ggammap d2h 9 r/w 0 set positive gamma curve for green 1 pkp1[2:0] pkp0[2:0] 00h 1 pkp3[2:0] pkp2[2:0] 00h 1 pkp5[2:0] pkp4[2:0] 00h 1 prp1[2:0] prp0[2:0] 00h
LG4572B ver. 1.0. 4 lge confidential 108 1 vrp0[4:0] 00h 1 vrp1[4:0] 00h 1 pfp1[2:0] pfp0[2:0] 00h 1 pfp3[2:0] pfp2[2:0] 00h 1 pmp[2:0] 00h ggamman d3h 9 r/w 0 set negative gamma curve for green 1 pkn1[2: 0] pkn0[2:0] 00h 1 pkn3[2:0] pkn2[2:0] 00h 1 pkn5[2:0] pkn4[2:0] 00h 1 prn1[2:0] prn0[2:0] 00h 1 vrn0[4:0] 00h 1 vrn1[4:0] 00h 1 pfn1[2:0] pfn0[2:0] 00h 1 pfn3[2:0] pfn2[2:0] 00h 1 pmn[2 :0] 00h bgammap d4h 9 r/w 0 set positive gamma curve for blue 1 pkp1[2:0] pkp0[2:0] 00h 1 pkp3[2:0] pkp2[2:0] 00h 1 pkp5[2:0] pkp4[2:0] 00h 1 prp1[2:0] prp0[2:0] 00h 1 vrp0[4:0] 00h 1 vrp1[4:0] 00h 1 pfp1[2:0] pfp0[2:0] 00h 1 pfp3[2:0] pfp2[2:0] 00h 1 pmp[2:0] 00h bgamman d5h 9 r/w 0 set negative gamma curve for blue 1 pkn1[2:0] pkn0[2:0] 00h 1 pkn3[2:0] pkn2[2:0] 00h 1 pkn5[2:0] pkn4[2:0] 00h 1 prn1[2:0] prn0[2:0] 00h 1 vrn0[4:0] 00h 1 vrn1[4:0] 00h 1 pfn1[2:0] pfn0[2:0] 00h 1 pfn3[2:0] pfn2[2:0] 00h 1 pmn[2:0] 00h
LG4572B ver. 1.0. 4 lge confidential 109 mddi e0h 6 r/w 0 mddi interface control 1 ref[2:0] lpm 30h ref C lpm =1: l ow p ower m ode enable d lpm=0: normal mode 1 txemp[1:0] txen 03h txemp - 00 : normal operation mode (2 ? ) - 01, 10 : overdrive mode (2.5 ? ) - 11 : overdrive mode (3 ? ) 1 data0_reset[5:0] 00h set data0 delay reset value 1 data1_reset[5:0] 0 4 h set data1 delay reset value 1 data1_offset[5:0] 02h set data1 delay offset value 1 stb_reset[5:0] 00h set strobe delay reset value memory e1h 4 r/w 0 f rame memory control 1 dcmr[1:0] 02h dc mr - memory refresh clock frequency 0: 1/ 48 , 1: 1/ 64 , 2: 1/ 96 , 3: 1/ 128 of oscillator freq 1 eccbyp 00h eccbyp C bypass ecc 1 ss[2:0] 02h ss - lcd clock frequency selection 1 opt [4:0] 00h opt C programmable options eeprom e2h 1 r/w 0 1 rfclk[3:0] eeprom 00h rfclk - i2c clock frequency [0..12] = (oscillator frequency)/ (16 C rfclk) eeprom C 1: external eeprom can be read, 0 : external eeprom cannot be read. test1 f0h 1 w 0 test register 1 1 hiz tpol[1:0] 00h hiz C vlout3 and vlout4 outputs to hi - z tpol C lcd polarity inversion control test2 f1h 1 w 0 memory bist control 1 balg[2:0] 00h balg - bist algorithm 2 errthr[7:0] 80h errthr - error count threshold 3 mdrt[7:0] 00h mdrt - memory data retention time otp1 f8h 3 w 0 1 ptm[1:0] prd pwe vpp pprog 00h ptm C pins for enabling test mode pwe C write ena ble pprog C program mode enable prd C read enable vpp C power control switch 1 aprg pa[1:0] 00h aprg C enable automatic program address decision ignoring register pa pa C write address 1 pdin[7:0] 00h pdin C data input otp2 f9h 1 w 0 ot p control 2 1 vcmsel[1:0] ra[1:0] 00h vcmsel C set vcom level from either the register c5h or the otp. ra C read address otp3 fah 4 r 0 otp control 3 1 pdout[7:0] xxh pdout C otp read data output 1 pdout[15:8] xxh
LG4572B ver. 1.0. 4 lge confidential 110 1 pdout[23:16] xxh 1 pdout[31:24] xxh
LG4572B ver. 1.0. 4 lge confidential 111 special command set for mipi dsi configuration data 0 data 1 default b7 b6 b5 b4 b3 b2 b1 b0 01h no_bta mode - hrx_freq ltx_clk ltx_ctl ltx_freq[1:0] 07h 02h ign_cer r 00h 03h hrx_to[7:0] 80h 04h ltx_to[7:0 ] c0h note : this special command set for mipi dsi configuration can only be set by dsi generic short write with 2 parameters. the dsi generic short write with 2 parameters packet form is as follows as shown earlier in mipi dsi introduction page. the descriptions for the above parameters are as follows. parameter name description no_bta bta (bus turn around) disable (default : 0) 0 : enable, 1 : disable mode dsi operation mode (default : 0) 0 : command mode, 1 : video mode this only applicable to frame memory inside ic such as lg 4572b . hrx_freq hs - rx frequency (default 0) write this, if needed, using lpdt prior to any hs - tx. this is used to detect hs sot and eot sequences 0 : 2.5ns load < 5pf, 1 : normal drivability ltx_freq [1:0] lp - tx frequency (def ault : 11b) 00 : lp - tx clock = 1/4 of hs - rx ddr clock 01 : lp - tx clock = 1/6 of hs - rx ddr clock 10 : lp - tx clock = 1/8 of hs - rx ddr clock 11 : lp - tx clock = 1/12 of hs - rx ddr clock ign_cerr ignore checksum error on the null packet and the blanking packet. (default : 0) 0 : checksum error ignored, 1 : checksum error cared. this bit is to support intel specific item (#9). l p s s o t l p s e o t d a t a i d e c c d a t a 0 d a t a 1 p a c k e t h e a d e r ( p h )
LG4572B ver. 1.0. 4 lge confidential 112 hrx_to[7:0] hs - rx timeout value in 16*rxbyteclkhs (default : 80h) rxbyteclkhs is a byte clock after multi - lane merge. ltx_to[7:0] lp - t x timeout value in 16*txclkesc (default : c0h)
LG4572B ver. 1.0. 4 lge confidential 113 6.2 command description 6.2.1 00h C no operation 00h no operation dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 0 0 0 0 0 - parameter none description this command is an empty comm and; it does not have any effect on the display module. however, it can be used to terminate memory write, memory read, memory write continue or memory read continue as described in ramwr (memory write), ramrd (memory read), ramwrc (memory write continue) and ramrdc (memory read continue) commands. restriction - flow chart -
LG4572B ver. 1.0. 4 lge confidential 114 6.2.2 01h C software reset 01h s oftware reset dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 0 0 0 0 1 - parameter none description when the softwa re reset command is written, it causes a software reset. it resets the commands and parameters to their default values. the display is blank immediately. restriction if a soft_reset is sent when the display module is in sleep mode, the host processor m ust wait 120 milliseconds before sending an exit_sleep_mode command. s oft_reset should not be sent during exit_sleep_mode sequence. no new command setting is allowed until the lg 4572b enters the sleep mode. see display on/off sequence for sequence to ent er sleep mode. if a soft_reset is sent when the display module is in sleep mode, data in nvm are read. no new command setting is inhibited when data are read (5ms). flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r s o f t _ r e s e t b l a n k d i s p l a y d e v i c e r e s e t t o s w d e f a u l t s s l e e p m o d e o n
LG4572B ver. 1.0. 4 lge confidential 115 6.2.3 0ah C read display power mode 0ah read displa y power mode dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 0 1 0 1 0 0ah parameter 1 1 x 0 idm pt l nsl p no r dis p 0 0 08 h descriptio n this command indicates the current status of the display as described below: bit descri ption comment command list symbol d6 idle mode on/off idm d5 partial mode on/off ptl d4 sleep mode on/off nslp d3 display normal mode on/off nor d2 display on/off disp ? bit d6 C idle mode on/off ? 0 ? = idle mode off ? 1 ? = idle mode on ? bit d5 C p artial mode on/off ? 0 ? = partial mode off ? 1 ? = partial mode on ? bit d4 C sleep mode ? 0 ? = sleep mode on ? 1 ? = sleep mode off ? bit d3 C display normal mode on/off ? 0 ? = display normal mode off ? 1 ? = display normal mode on ? bit d2 C display on/off ? 0 ? = dis play off ? 1 ? = display on restriction -
LG4572B ver. 1.0. 4 lge confidential 116 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r g e t _ p o w e r _ m o d e h o s t l g 4 5 7 2 d u m m y r e a d s e n d 1 s t p a r a m e t e r
LG4572B ver. 1.0. 4 lge confidential 117 6.2.4 0bh C read display madctl 0bh read display madctl dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 0 1 0 1 1 0bh parameter 1 1 x my mx mv 0 bgr 0 fh fv 00h description this command indicates the current status of the display as described below: bit description comment command list symbol d7 page address order my d6 column address order mx d5 page/column order mv d3 rgb/bgr o rder bgr d1 flip horizontal fh d0 flip vertical fv ? bit d7 C page address order ? 0 ? = top to bottom (when set_address_mode d7= ? 0 ? ) ? 1 ? = bottom to top (when set_address_mode d7= ? 1 ? ) ? bit d6 C column address order ? 0 ? = left to right (when set_a ddress_mode d6= ? 0 ? ) ? 1 ? = right to left (when set_address_mode d6= ? 1 ? ) ? bit d5 C page/column order ? 0 ? = normal mode (when set_address_mode d5= ? 0 ? ) ? 1 ? = reverse mode (when set_address_mode d5= ? 1 ? ) ? bit d3 C rgb/bgr order ? 0 ? = pixel in rgb order (when set_address_mode d3= ? 0 ? ) ? 1 ? = pixel in bgr order (when set_address_mode d3= ? 1 ? ) ? bit d1 C flip horizontal ? 0 ? = normal (when set_address_mode d1= ? 0 ? ) ? 1 ? = flip (when set_address_mode d1= ? 1 ? ) ? bit d0 C flip vertical ? 0 ? = normal (when set_address_mod e d0= ? 0 ? ) ? 1 ? = flip (when set_address_mode d0= ? 1 ? ) x = don ? t care
LG4572B ver. 1.0. 4 lge confidential 118 restriction - flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r g e t _ p o w e r _ m o d e h o s t l g 4 5 7 2 d u m m y r e a d s e n d 1 s t p a r a m e t e r
LG4572B ver. 1.0. 4 lge confidential 119 6.2.5 0ch C read display pixel format 0ch read display pixel format dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 0 1 1 0 0 0ch parameter 1 1 x 0 dpipf[2:0] 0 dbipf[2:0] 77h description this command indicates the current status of the display as described below: bit description comment command list symbol d6 dpipf (rgb interface color format) d5 d4 d2 dbipf (system interface color format) d1 d0 ? bit d[6:4] C dpi pixel format (rgb interface color format selection) ? bit d[2:0] C dbi pixel format(system interface color format selection) see description of command set_pixe l_format(3ah). control interface color format d6/d2 d5/d1 d4/d0 setting disabled 0 0 0 setting disabled 0 0 1 setting disabled 0 1 0 setting disabled 0 1 1 setting disabled 1 0 0 16bit/pixel (65 k colors) 1 0 1 18bit/pixel (262k colors ) 1 1 0 24bit/pixel (16m clors) 1 1 1 x = don ? t care restriction -
LG4572B ver. 1.0. 4 lge confidential 120 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r g e t _ p i x e l _ f o r m a t h o s t l g 4 5 7 2 d u m m y r e a d s e n d 1 s t p a r a m e t e r
LG4572B ver. 1.0. 4 lge confidential 12 1 6.2.6 0dh C read display image mode 0dh read display image mode dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 0 1 1 0 1 0dh parameter 1 1 x 0 0 inv 0 0 0 0 0 00h description the display module returns the current status of the display as described in the table below. bit description comment command list symbol d5 inversion on/off inv ? ? bit d5 C inversio n on/off ? 0 ? = inversion off ? 1 ? = inversion on x = don ? t care restriction - flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r g e t _ d i s p l a y _ m o d e h o s t l g 4 5 7 2 d u m m y r e a d s e n d 1 s t p a r a m e t e r
LG4572B ver. 1.0. 4 lge confidential 122 6.2.7 0d h C read display image mode 0dh read display image mode dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 0 1 1 0 1 0dh parameter 1 1 x 0 0 in v 0 0 0 0 0 00h descriptio n the display module returns the current status of the display as described in the table below. bit descriptio n comment command list symbol d5 inversion on/off inv ? ? bit d5 C inversion on/off ? 0 ? = inversion off ? 1 ? = inversion on x = don ? t care restriction - flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r g e t _ d i s p l a y _ m o d e h o s t l g 4 5 7 2 d u m m y r e a d s e n d 1 s t p a r a m e t e r
LG4572B ver. 1.0. 4 lge confidential 123 6.2.8 0eh C read display signal mode 0eh read display signal mode dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 0 1 1 1 0 0eh parameter 1 1 x te tem 0 0 0 0 0 0 00h description the display module returns the current status of the display as described in the table below. bit description comment command list symbol d7 tearing effect line on/of f te d6 tearing effect line output mode tem ? ? bit d7 C tearing effect line on/off ? 0 ? = tearing effect line off ? 1 ? = tearing effect on ? bit d6 C tearing effect line output mode ? 0 ? = mode 1 ? 1 ? = mode 2 x = don ? t care restriction -
LG4572B ver. 1.0. 4 lge confidential 124 flow char t l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r g e t _ d i s p l a y _ m o d e h o s t l g 4 5 7 2 d u m m y r e a d s e n d 1 s t p a r a m e t e r
LG4572B ver. 1.0. 4 lge confidential 125 6.2.9 10h C sleep in 10h sleep in dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 1 0 0 0 0 10h parameter none description this command causes the display module to enter the minimum power consu mption mode. in this mode e.g. the dc/dc converter is stopped, internal oscillator is stopped, and panel scanning is stopped. hos t interface and memory are still working and the memory can or cannot keep its contents. backlights, display and keyboard, are off. dimming function does not work when there is changing mode from sleep out to sleep in. restriction this command has no effect when module is already in sleep in mode. sleep in mode can only be left by the sleep out command (11h) . it will be necessa ry to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. it will be necessary to wait 120msec after sending sleep out command (when in sleep in mode) before sleep in command can be sent. flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n a n y m o d e s e q u e n t i a l t r a n s f e r m o d e e n t e r _ s l e e p _ m o d e b l a n k d i s p l a y d e v i c e p o w e r o f f d i s p l a y d e v i c e s t o p p o w e r s u p p l y s t o p i n t e r n a l o s c i l l a t o r s l e e p m o d e
LG4572B ver. 1.0. 4 lge confidential 126 6.2.10 11h C sleep out 11h sleep out dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 1 0 0 0 1 11h parameter none description this command turns off sleep mode. in this mode e.g. the dc/dc converter is enabled, internal oscillator is started, and panel scanning is started. restriction this command has no effect when module is already in sleep out mode. sleep out mode can only be left by the sleep in command (10h), sw reset command (01h) o r hw reset. it will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. the display module loads all display supplier?s factory default values to the registers during this t ime and there cannot be any abnormal visual effect on the display image if factory default and register values are same when this load is done and when the display module is already sleep out mode. the display module is doing self - diagnostic functions duri ng this 5msec. it will be necessary to wait 120msec after sending sleep in command (when in sleep out mode) before sleep out command can be sent. flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s l e e p m o d e s e q u e n t i a l t r a n s f e r m o d e e x i t _ s l e e p _ m o d e s t a r t i n t e r n a l o s c i l l a t o r p o w e r o n d i s p l a y d e v i c e s t a r t p o w e r s u p p l y b l a n k d i s p l a y d e v i c e d i s p l a y m e m o r y c o n t e n t s s l e e p m o d e o f f
LG4572B ver. 1.0. 4 lge confidential 127 6.2.11 12h C partial mode on 12h partial mode on dcx rdx wrx d [23:8] d 7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 1 0 0 1 0 12h parameter none description this command causes the lcd module to enter the partial mode. the partial display mode window is described by the set_partial_area command (30h). to leave pa rtial display mode, the enter_normal_mode (13h) should be written. restriction this command has no effect when partial mode is active. flow chart see flow chart of command set_partial_area(30h).
LG4572B ver. 1.0. 4 lge confidential 128 6.2.12 13h C normal display mode on 13h normal display mode o n dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 0 1 0 0 1 1 13h parameter none description this command returns the display to normal mode. normal display mode on means partial mode off. note : when a command breaks in the middle of frame period in partial mode, that command becomes valid from the next frame period. restriction this command has no effect when normal mode is already active. flow chart see flow chart of command set_partial_area(30h).
LG4572B ver. 1.0. 4 lge confidential 129 6.2.13 20h C display i nversion off 20h display inversion off dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 0 0 0 0 0 20h parameter none description this command is used to recover from display inversion mode. this command makes no change of co ntents of frame memory. this command does not change any other status. (example) x = don ? t care restriction this command has no effect when the module is already in inversion off. m e m o r y d i s p l a y
LG4572B ver. 1.0. 4 lge confidential 130 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r i n v e r t m o d e o n e x i t _ i n v e r t _ m o d e i n v e r t m o d e o f f
LG4572B ver. 1.0. 4 lge confidential 131 6.2.14 21 h C display inversion on 21h display inversion on dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 0 0 0 0 1 21h parameter none description this command is used to enter into display inversion mode. this command makes no change of contents of frame memory. every bit is inverted from the frame memory to the display. this command does not change any other status. (example) x = don ? t care restriction this command has no effect when the d isplay module is already inverting the display image. m e m o r y d i s p l a y
LG4572B ver. 1.0. 4 lge confidential 132 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r i n v e r t m o d e o f f e n t e r _ i n v e r t _ m o d e i n v e r t m o d e o n
LG4572B ver. 1.0. 4 lge confidential 133 6.2.15 28h C display off 28h display off dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 0 1 0 0 0 28h parameter none description t his command is used to enter into display off mode. in this mode, the output from f rame m emory is disabled and either normal white or normal black display will be made . this command makes no change of contents of frame memory. this command does not change any other status. there will be no abnormal visible effect on the display. (example) x = don ? t care restriction this command has no effect when the displa y panel is already off. m e m o r y d i s p l a y
LG4572B ver. 1.0. 4 lge confidential 134 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r d i s p l a y p a n e l o n s e t _ d i s p l a y _ o f f d i s p l a y p a n e l o f f
LG4572B ver. 1.0. 4 lge confidential 135 6.2.16 29h C display on 29h display on dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 0 1 0 0 1 29h parameter none description this command is used to recover from display off mode. output from the frame memory is enabled. this command makes no change of contents of frame memory. this command does not change any other status. (example) x = don ? t care restriction this command has no effect when module is already in display on mode. m e m o r y d i s p l a y
LG4572B ver. 1.0. 4 lge confidential 136 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r d i s p l a y p a n e l o f f s e t _ d i s p l a y _ o n d i s p l a y p a n e l o n
LG4572B ver. 1.0. 4 lge confidential 137 6.2.17 2a h C column address set 2ah column address set dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 0 1 0 1 0 2ah 1 st parameter 1 1 x 0 0 0 0 0 0 sc[9:8] 000h 2 nd parameter 1 1 x sc[7:0] 3 rd pa rameter 1 1 x 0 0 0 0 0 0 ec[9:8] 1dfh 4 th parameter 1 1 x ec[7:0] description this command defines the column extent of the frame memory accessed by the host processor. the values of sc[ 9 :0] and ec[ 9 :0] are referred when write_memory_start (2ch) a nd read_memory_start (2eh) commands are written. no status bits are changed. (example) x = don ? t care restriction sc [ 9 :0] must be equal to or less than ec[ 9 :0]. if sc[9:0] or ec[9:0] is greater than the available frame m emory then the parameter is not updated. set the 1st parameter b5 in s et_address_mode (36h) in advance. note: the parameters are disregarded in following cases. ? if set_address_mode b5 = 0: sc[ 9 :0] or ec[ 9 :0] 1df h ? if set_address_mode b5 = 1: sc[ 9 :0] or ec[ 9 :0] 35 fh s c [ 9 : 0 ] e c [ 9 : 0 ]
LG4572B ver. 1.0. 4 lge confidential 138 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e s e t _ c o l u m n _ a d d r e s s 1 s t & 2 n d p a r a m e t e r s c [ 9 : 0 ] 3 r d & 4 t h p a r a m e t e r e c [ 9 : 0 ] s e t _ p a g e _ a d d r e s s 1 s t & 2 n d p a r a m e t e r s p [ 9 : 0 ] 3 r d & 4 t h p a r a m e t e r e p [ 9 : 0 ] w r i t e _ m e m o r y _ s t a r t i m a g e d a t a d 1 [ 9 : 0 ] , d 2 [ 9 : 0 ] d n [ 9 : 0 ] n e x t c o m m a n d a s r e q u i r e d
LG4572B ver. 1.0. 4 lge confidential 139 6.2.18 2b h C page address set 2bh page address set dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 0 1 0 1 1 2bh 1 st parameter 1 1 x 0 0 0 0 0 0 sp[9:8] 000h 2 nd param eter 1 1 x sp[7:0] 3 rd parameter 1 1 x 0 0 0 0 0 0 ep[9:8] 35fh 4 th parameter 1 1 x ep[7:0] description this command defines the page extent of the frame memory accessed by the host processor. no status bits are changed. the values of sp[ 9 :0] a nd ep[ 9 :0] are referred when write_memory_start (2ch) and read_memory_start (2eh) commands are written. (example) x = don ? t care restriction sp[ 9 :0] must always be equal to or less than ep[ 9 :0]. if sp[9:0] or ep[9:0] is greater than the available frame memory then the parameter is not updated. set the 1st parameter b5 in set_address_mode (36h) in advance. note: the parameters are disregarded in following cases. ? if set_address_mode b5 = 0: sp[ 9 :0] or ep[ 9 :0] 35 fh ? if set_address_mode b5 = 1: sp[ 9 :0] or ep[ 9 :0] 1df h s p [ 9 : 0 ] e p [ 9 : 0 ]
LG4572B ver. 1.0. 4 lge confidential 140 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e s e t _ c o l u m n _ a d d r e s s 1 s t & 2 n d p a r a m e t e r s c [ 9 : 0 ] 3 r d & 4 t h p a r a m e t e r e c [ 9 : 0 ] s e t _ p a g e _ a d d r e s s 1 s t & 2 n d p a r a m e t e r s p [ 9 : 0 ] 3 r d & 4 t h p a r a m e t e r e p [ 9 : 0 ] w r i t e _ m e m o r y _ s t a r t i m a g e d a t a d 1 [ 9 : 0 ] , d 2 [ 9 : 0 ] d n [ 9 : 0 ] n e x t c o m m a n d a s r e q u i r e d
LG4572B ver. 1.0. 4 lge confidential 141 6.2.19 2c h C w rite memory start 2ch w rite memory start dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 0 1 1 0 0 2ch 1 st parameter 1 1 d1[23:0] - 2 nd parameter 1 1 d2[23:0] - : : 1 1 : : - n th parameter 1 1 dn[23:0] - description this command transfers image data from the host processor to the display module?s frame memory starting at the pixel location specified by preceding set_column_address and set_page_address commands. the column and page registers are reset to the start column (sc) and start page (sp), respectively. pixel data 1 is stored in frame memory at (sc, sp). the column register is then incremented and pixels are written to the frame memory until the column register equals the end column (ec) value. the column register is then reset to sc and the page register is incremented. pixels are written to the frame memory until the page register equals the end page (ep) v alue and the column register equals the ec value, or the host processor sends another command. if the number of pixels exceeds (ec C sc + 1) * (ep C sp + 1) the extra pixels are over write. restriction a write_memory_start should follow a set_column_add ress, set_page_address or set_address_mode to define the write location. otherwise, data written with write_memory_start and any following write_memory_continue commands is written to undefined locations.
LG4572B ver. 1.0. 4 lge confidential 142 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e w r i t e _ m e m o r y _ s t a r t i m a g e d a t a d 1 [ 2 3 : 0 ] , d 2 [ 2 3 : 0 ] d n [ 2 3 : 0 ] n e x t c o m m a n d
LG4572B ver. 1.0. 4 lge confidential 143 6.2.20 2e h C read memory start 2eh read memory start dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 0 1 1 1 0 2eh 1 st parameter 1 1 d1[23:0] - 2 nd parameter 1 1 d2[23:0] - : : 1 1 : : - n th parameter 1 1 dn[23:0] - description this command transfers image data from the display modules frame memory to the host processor starting at the pixel location specified by preceding set_column_address and set_page_address commands . the column and page registers are reset to the start co lumn (sc) and start page (sp), respectively. pixels are read from frame memory at (sc, sp). the column register is then incremented and pixels read from the frame memory until the column register equals the end column (ec) value. the column register is the n reset to sc and the page register is incremented. pixels are read from the frame memory until the page register equals the end page (ep) value and the column register equals the ec value, or the host processor sends another command. restriction regardl ess of the color mode set in set_pixel_format, the pixel format returned by r ead_memory_continue is always 24 - bit so there is no restriction on the length of data.
LG4572B ver. 1.0. 4 lge confidential 144 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e r e a d _ m e m o r y _ s t a r t i m a g e d a t a d 1 [ 2 3 : 0 ] , d 2 [ 2 3 : 0 ] d n [ 2 3 : 0 ] n e x t c o m m a n d d u m m y r e a d
LG4572B ver. 1.0. 4 lge confidential 145 6.2.21 3 0 h C partial area definition 30h partial area definition dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 1 0 0 0 0 30h 1 st parameter 1 1 x 0 0 0 0 0 0 sr[9:8] 000h 2 nd parameter 1 1 x sr[7:0] 3 rd parameter 1 1 x 0 0 0 0 0 0 er[9:8] 35fh 4 th parameter 1 1 x er[7 :0]
LG4572B ver. 1.0. 4 lge confidential 146 description this command defines the partial mode?s display area. there are 2 parameters ? restriction sr[ 9 :0] and er[ 9 :0] must not b e greater than 35 fh. the bits other than sr[ 9 :0] and er[ 9 :0] are don?t care. p a r t i a l a r e a s r [ 9 : 0 ] e r [ 9 : 0 ] p a r t i a l a r e a e r [ 9 : 0 ] s r [ 9 : 0 ] p a r t i a l a r e a
LG4572B ver. 1.0. 4 lge confidential 147 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e s e t _ p a r t i a l _ a r e a a n y m o d e 1 s t & 2 n d p a r a m e t e r s r [ 9 : 0 ] 3 r d & 4 t h p a r a m e t e r e r [ 9 : 0 ] e n t e r _ p a r t i a l _ m o d e p a r t i a l m o d e o n 1 . t o e n t e r p a r t i a l m o d e 2 . t o e x i t p a r t i a l m o d e s e t _ d i s p l a y _ o f f p a r t i a l m o d e o n n o r m a l m o d e o n e n t e r _ n o r m a l _ m d o e w r i t e _ m e m o r y _ s t a r t i m a g e d a t a d 1 [ 2 3 : 0 ] , d 2 [ 2 3 : 0 ] d n [ 2 3 : 0 ] s e t _ d i s p l a y _ o n e n t e r n o r m a l m o d e t u r n s p a r t i a l m o d e o f f o p t i o n a l ( t o a v o i d t e a r i n g e f f e c t )
LG4572B ver. 1.0. 4 lge confidential 148 6.2.22 3 4 h C tearing effect line off 34h tearing effect line off dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 1 0 1 0 0 34h parameter none description this command turns off the tearing effect output signal from the te signal line. x = don?t care restriction this command has no effect when tearing effect output is already off. flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e s e t _ t e a r _ o f f t e o u t p u t o n o r o f f t e o u t p u t o f f
LG4572B ver. 1.0. 4 lge confidential 149 6.2.23 3 5 h C tearing effect line on 35h tearing effect line on dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 1 0 1 0 1 35h parameter 1 1 x 0 0 0 0 0 0 0 tem 00h description this command turns on the display modul e?s tearing effect output signal on the te signal line. the tearing effect line on has one parameter, te on, that describes the tearing effect output line mode. see te pin output signal for detail. tem = 0: the tearing effect output line consists of v - bl anking information only. the tearing effect output line shall be high during vertical blanking period. tem = 1: the tearing effect output line consists of both v - blanking and h - blanking information. vertical blanking period: non - lit display period in (back porch + front porch) note: the tearing effect output line shall be active low when the display module is in sleep mode. x = don?t care restriction this command has no effect when tearing effect output is already on. changes in parameter tem is enable from the next frame period. t v d l t v d h t e t v d l t v d h t e t h d l t h d h
LG4572B ver. 1.0. 4 lge confidential 150 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e s e t _ t e a r _ o n t e o u t p u t o n o r o f f t e o u t p u t o n 1 s t p a r a m e t e r t e l o m
LG4572B ver. 1.0. 4 lge confidential 151 6.2.24 3 6 h C memory access control 36h memory access control dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 1 0 1 1 0 36h parameter 1 1 x my mx m v 0 bg r 0 fh fv 00h 36 descript ion the display module returns the current power mode. description comment command list symbol d7 page address order my d6 column address order mx d5 page/column order mv d3 rgb/bgr order bgr d1 flip horizontal fh d0 flip vertical fv
LG4572B ver. 1.0. 4 lge confidential 152 ? my C ? ? ? ? ? mx C ? ? ? ? s p e p s e c c h o s t p r o c e s s o r s p e p s e c c f r a m e m e m o r y m y = 0 s p e p s e c c h o s t p r o c e s s o r e p s p s e c c f r a m e m e m o r y m y = 1 m x = 0 m v = 0 b g r = x s p e p s e c c h o s t p r o c e s s o r s p e p s e c c f r a m e m e m o r y m x = 0 s p e p s e c c h o s t p r o c e s s o r s p e p e s c c f r a m e m e m o r y m x = 1 m y = 0 m v = 0 b g r = x
LG4572B ver. 1.0. 4 lge confidential 153 ? mv C ? ? ? ? ? bgr C ? ? ? ? ? fv C ? ? ? ? ? fh C ? ? ? ? s p e p s e c c h o s t p r o c e s s o r s p e p s e c c f r a m e m e m o r y m v = 0 s p e p s e c c h o s t p r o c e s s o r s c e c s e p p f r a m e m e m o r y m v = 1 m y = 0 m x = 0 b g r = x 1 n 1 m f r a m e m e m o r y 1 n d i s p l a y d e v i c e b g r = 0 1 n f r a m e m e m o r y b g r = 1 1 m 1 m 1 n f r a m e m e m o r y 1 n 1 m f r a m e m e m o r y 1 n d i s p l a y d e v i c e f v = 0 1 n f r a m e m e m o r y n 1 d i s p l a y d e v i c e f v = 1 m l = 0 f h = 0 1 m 1 m 1 m 1 n 1 m f r a m e m e m o r y 1 n d i s p l a y d e v i c e f h = 0 1 n f r a m e m e m o r y 1 n d i s p l a y d e v i c e f h = 1 m l = 0 f v = 0 1 m 1 m m 1
LG4572B ver. 1.0. 4 lge confidential 154 host processor display image d 7 d 6 d 5 note m y m x m v 0 0 0 normal 1 0 0 flip vertical 0 1 0 flip horizontal
LG4572B ver. 1.0. 4 lge confidential 155 1 1 0 180
LG4572B ver. 1.0. 4 lge confidential 156 1 1 1 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e s e t _ a d d r e s s _ m o d e a d d r e s s m o d e n e w a d d r e s s m o d e 1 s t p a r a m e t e r b 7 , b 6 , b 5 , b 4 , b 3 , b 2 , b 1 , b 0
LG4572B ver. 1.0. 4 lge confidential 157 6.2.25 3ah C interface pixel format 3ah interface pixel format dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 1 1 0 1 0 3ah parameter 1 1 x 0 dpipf [2:0] 0 dbi pf [2:0] 77h description this command is used to define the format of rgb picture data, which are to be transferred via the dbi/dpi. the formats are shown in the following table: bit d[6:4] C dpi pixel format (rgb interface color format selection) bit d [ 2 : 0 ] C d b i pixel format ( i80, m68 interface color format selection) control interface color format d6/d2 d5/d1 d4/d0 setting disabled 0 0 0 setting disabled 0 0 1 setting disabled 0 1 0 setting disabled 0 1 1 setting disabled 1 0 0 16b it/pixel (65 k colors) 1 0 1 18bit/pixel (262k colors) 1 1 0 24bit/pixel (16m colors) 1 1 1 see dpi data format data format list for each type of interfaces. see d b i data format data format list for each type of interfaces. note 1: when the s etting disabled bits are set, undesirable image will be displayed on the panel. x = don ? t care restriction -
LG4572B ver. 1.0. 4 lge confidential 158 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e s e t _ p i x e l _ f o r m a t n b p p m o d e p a r a m t e r n e w m b p p m o d e
LG4572B ver. 1.0. 4 lge confidential 159 6.2.26 3ch C write memory continue 3ch write memory continue dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 0 1 1 0 0 2ch 1 st parameter 1 1 d1[23:0] - 2 nd parameter 1 1 d2[23:0] - : : 1 1 : : - n th parameter 1 1 dn[23:0] - description this command transfers image data from the host processor to the display module?s frame memory continuing from the pixel location following the previous write_memory_continue or write_memory_start command. data is written continuing from the pixel location after the write range of the previous write_memory_start or write_memory_continu e. the column register is then incremented and pixels are written to the frame memory until the column register equals the end column (ec) value. the column register is then reset to sc and the page register is incremented. pixels are written to the frame memory until the page register equals the end page (ep) value and the column register equals the ec value, or the host processor sends another command. if the number of pixels exceeds (ec C sc + 1) * (ep C sp + 1) the extra pixels are over write. restric tion a write_memory_start should follow a set_column_address, set_page_address or set_address_mode to define the write address. otherwise, data written with write_memory_continue is written to undefined addresses.
LG4572B ver. 1.0. 4 lge confidential 160 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e w r i t e _ m e m o r y _ s t a r t i m a g e d a t a d 1 [ 2 3 : 0 ] , d 2 [ 2 3 : 0 ] d n [ 2 3 : 0 ] n e x t c o m m a n d
LG4572B ver. 1.0. 4 lge confidential 161 6.2.27 3 e h C read memory continue 3eh read memory continue dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 0 1 0 1 1 1 0 3eh 1 st parameter 1 1 d1[23:0] - 2 nd parameter 1 1 d2[23:0] - : : 1 1 : : - n th parameter 1 1 dn[23:0] - description this command transfers image data from the display modules frame memory to the host processor continuing from the location following the previous read_memory_continue or read_memory_start command. pixels are read continuing from the pix el location after the read range of the previous read_memory_start or read_memory_continue. the column register is then incremented and pixels are read from the frame memory until the column register equals the end column (ec) value. the column register is then reset to sc and the page register is incremented. pixels are read from the frame memory until the page register equals the end page (ep) value and the column register equals the ec value, or the host processor sends another command. restriction r egardless of the color mode set in set_pixel_format, the pixel format returned by read_memory_continue is always 24 - bit so there is no restriction on the length of data.
LG4572B ver. 1.0. 4 lge confidential 162 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e r e a d _ m e m o r y _ s t a r t i m a g e d a t a d 1 [ 2 3 : 0 ] , d 2 [ 2 3 : 0 ] d n [ 2 3 : 0 ] n e x t c o m m a n d d u m m y r e a d
LG4572B ver. 1.0. 4 lge confidential 163 6.2.28 44 h C set tear scan line 44h set tear sca n line dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 1 0 0 0 1 0 0 44h 1 st parameter 1 1 x 0 0 0 0 0 0 ten[9:8] 00h 2 nd parameter 1 1 x ten [7:0] 00h description this command turns on the display module?s tearing effect ou tput signal on the te signal line when the display module reaches line n defined by tel [ 9 :0]. te line is unaffected by change in b4 bit of set_address_mode command. see figure in te pin output signal. x = don ? t care restriction the command takes affect on the frame following the current frame. therefore, if the te signal is already on, te signal is output according to the old set_tear_on and s et_tear_scanline commands until the end of currently scanned frame. setting is disabled when tem=1 of s et_tear_on (35h). make sure that te n [ 9 :0] < nl (number of line) . flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e t e o u t p u t o n o r o f f s e t _ t e a r _ s c a n l i n e 1 s t & 2 n d p a r a m e t e r s t s [ 8 : 0 ] t e o u t p u t o n t h e n t h l i n e
LG4572B ver. 1.0. 4 lge confidential 164 6.2.29 45 h C get scan line 45h get scan line dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 1 0 0 0 1 0 1 45h 1 st parameter 1 1 x 0 0 0 0 0 0 rdn[9:8] xxh 2 nd parameter 1 1 x rdn[7:0] xxh description the display module returns the current scan line. the total number of scan lines is defined as (bp + nl + fp). the first scan line of back portch period is defined as line 0. in sleep mode, the value returned by get_scanline is undefined. x = don ? t care restriction after get_scanline command is input, it takes 3us or more to read it. after parameters are read, wait 3 us or more to reinput this command. 3 u s 3 u s w r x r d x 4 5 h d u m m y r d n [ 9 : 8 ] r d n [ 7 : 0 ] 4 5 h d b [ 7 : 0 ]
LG4572B ver. 1.0. 4 lge confidential 165 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r g e t _ d i a g n o s t i c _ r e s u l t d u m m y r e a d s e n d 1 s t p a r a m e t e r r d n [ 9 : 8 ] h o s t l g 4 5 7 2 w a i t 3 u s s e n d 2 n d p a r a m e t e r r d n [ 7 : 0 ]
LG4572B ver. 1.0. 4 lge confidential 166 6.2.30 51h C write display brightness 51h write display brightness dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 1 0 1 0 0 0 1 51h 1 st parameter 1 1 x dbv [7:0] 00h descriptio n this command is used to adjust the brightness value of the display. it should be checked what the relationship between this written value and output brightness of the display is. this relationship is defined on the display module specification. in princ iple relationship is that 00h value means the lowest brightness and ffh value means the highest brightness. x = don ? t care restriction - flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e w r d i s b v d b v [ 8 . . 0 ] n e w d i s p l a y l u m i n a n c e v a l u e l o a d e d
LG4572B ver. 1.0. 4 lge confidential 167 6.2.31 52h C read display brightness value 52h read display brightness value dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 1 0 1 0 0 1 0 52h 1 st parameter 1 1 x x x x x x x x x xxh 2 nd parameter 1 1 x dbv[7:0] 00h description this command returns the brightness value of the display. it should be c hecked what the relationship between this returned value and output brightness of the display. this relationship is defined on the display module specification is. in principle the relationship is that 00h value means the lowest brightness and ffh value me ans the highest brightness. x = don ? t care restriction -
LG4572B ver. 1.0. 4 lge confidential 168 flow chart r e a d r d d i s b v s e n d 2 n d p a r a m e t e r l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r r e a d r d d i s b v d u m m y r e a d s e n d 2 n d p a r a m e t e r h o s t d i s p l a y s e r i a l i / f m o d e p a r a l l e l i / f m o d e
LG4572B ver. 1.0. 4 lge confidential 169 6.2.32 53h C write control display 53h write control display dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 1 0 1 0 0 1 1 53h 1 st parameter 1 1 x 0 0 bctrl 0 dd bl 0 0 00h description this command is used to control display brightness. bctrl: brightness control block on/off, this bit is always used to switch brightness for display. 0 = off (brightness registers are 00h, dbv[7..0 ]) 1 = on (brightness registers are active, according to the other parameters.) display dimming ( dd ): (only for manual brightness setting) dd = 0: display dimming is off dd = 1: display dimming is on bl : backlight control on/off 0 = off (completely turn off backlight circuit. control lines must be low. ) 1 = on dimming function is adapted to the brightness registers for display when bit bctrl is changed at dd=1, e.g. bctrl: 0 ? 1 or 1 ? 0. when bl bit change from on to off, backlight is turned off w ithout gradual dimming, even if dimming - on (dd=1) are selected. x = don?t care. restriction -
LG4572B ver. 1.0. 4 lge confidential 170 flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e w r c t r l d b c t r l , d d , b l n e w c o n t r o l v a l u e l o a d e d
LG4572B ver. 1.0. 4 lge confidential 171 6.2.33 54 h C read control display 54h read control display dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 1 0 1 0 1 0 0 54h 1 st parameter 1 1 x x x x x x x x x xxh 2 nd parameter 1 1 x 0 0 bctrl 0 0 dd bl 0 00h description this command returns ambient light and brightness control values . bctrl : brightness control block on/off, this bit is al ways used to switch brightness for display. 0 = off 1 = on display dimming ( dd ): dd = 0: display dimming is off dd = 1: display dimming is on bl : backlight control on/off 0 = off (completely turn off backlight circuit) 1 = on x = don?t care. restrict ion - flow chart r e a d r d c t r l d s e n d 2 n d p a r a m e t e r l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r r e a d r d c t r l d d u m m y r e a d s e n d 2 n d p a r a m e t e r h o s t d i s p l a y s e r i a l i / f m o d e p a r a l l e l i / f m o d e
LG4572B ver. 1.0. 4 lge confidential 172 6.2.34 55h C write content adaptive brightness control 55h write content adaptive brightness control dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 1 0 1 0 1 0 1 55h 1 st parameter 1 1 x 0 0 0 0 0 0 cabc[1:0] 00h description this command is used to set parameters for image content based adaptive brightness control functionality. there is possible to use 4 different modes for content adaptive image functionality, cabc[1:0] descripti on 2 ? h0 off 2 ? h1 user interface image 2 ? h2 still picture 2 ? h3 moving image x = don?t care. restriction - flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e w r c a b c 1 s t p a r a m e t e r : c a b c [ 1 : 0 ] n e w c o n t r o l v a l u e l o a d e d
LG4572B ver. 1.0. 4 lge confidential 173 6.2.35 56h C read content adaptive brightness control 56h read content adaptive brightness control dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 1 0 1 0 1 1 0 56h 1 st parameter 1 1 x x x x x x x x x xxh 2 nd parameter 1 1 x 0 0 0 0 0 0 cabc [1:0] 00 description this command is used to read the settings for image content b ased adaptive brightness control functionality. there is possible to use 4 different modes for content adaptive image functionality, cabc[1:0] description 2 ? h0 off 2 ? h1 user interface image 2 ? h2 still picture 2 ? h3 moving image x = don ? t care restriction - flow chart r e a d r d c a b c s e n d 2 n d p a r a m e t e r l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r r e a d r d c a b c d u m m y r e a d s e n d 2 n d p a r a m e t e r h o s t d i s p l a y s e r i a l i / f m o d e p a r a l l e l i / f m o d e
LG4572B ver. 1.0. 4 lge confidential 174 6.2.36 5eh C write cabc minimum brightness 5eh write cabc minimum brightness dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 1 0 1 1 1 1 0 5eh 1 st parameter 1 1 x cmb[7:0] 00 h description this command is used to set the minimum brightness value of the display for cabc function. in principle relationship is that 00h value means the lowest brightness for cabc and ffh value means the highest brightness for cabc. x = don ? t care restriction - flow chart l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n s e q u e n t i a l t r a n s f e r m o d e w r c a b c m b c m b [ 7 . . 0 ] n e w c o n t r o l v a l u e l o a d e d
LG4572B ver. 1.0. 4 lge confidential 175 6.2.37 5fh C read cabc minimum brightness 5fh read cabc minimum brightness dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 0 1 0 1 1 1 1 1 5fh 1 st parameter 1 1 x x x x x x x x x xxh 2 nd parameter 1 1 x cmb[7:0] 00 description this command returns the minimum brightness value of cabc function. in principle the relationship is that 00h value means the lowest brightness and ffh value means the highest brightness. cmb[7:0] is cabc minimum brightness specified with 9.2.45 write cabc minimum brightness (5eh) command. restriction - flow chart r e a d r d c a b c m b s e n d 2 n d p a r a m e t e r l e g e n d c o m m a n d p a r a m e t e r d i s p l a y a c t i o n m o d e s e q u e n t i a l t r a n s f e r r e a d r d c a b c m b d u m m y r e a d s e n d 2 n d p a r a m e t e r h o s t d i s p l a y s e r i a l i / f m o d e p a r a l l e l i / f m o d e
LG4572B ver. 1.0. 4 lge confidential 176 6.2.38 a1h C read ddb start mnemonic rdddb type read parameters no. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reset 1 ddb[ 7:0] : revision 10h 2 ddb[7:0] : level 01h 3 ddb[7:0] : not used 00h 4 ddb[7:0] : not used 00h 5 ddb[7:0] : manufacture id (msb) 01h 6 ddb[7:0] : manufacture id (lsb) 2ah 7 ddb[7:0] : device code (msb) 45h 8 ddb[7:0] : device code (lsb) 72h 9 ddb[ 7:0] : length of ddb level 2 data (msb) 00h 10 ddb[7:0] : length of ddb level 2 data (lsb) 2ah description this command returns the ddb (device descriptor block) values. for further ddb values in level 2 (larger number than 10) are not describ ed here in detail.
LG4572B ver. 1.0. 4 lge confidential 177 6.2.39 b1h C rgb interface setting b 1h rgb interface setting dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 0 1 1 0 0 0 1 b1h 1 st parameter 1 #a #b x dpicc sync ckpl hspl vspl depl 06h 2 nd parameter 1 #a #b x hbp [6:0 ] 1eh 3 rd parameter 1 #a #b x vbp [7:0] 0ch descriptio n this command is used to set registers related with rgb (mipi dpi) interface. sync C sync mode 0 = vsync+hsync+de 1 = vsync+hsync if sync is 1, the de pin is ignored and a corresponding signal i s internally generated using the registers hbp and vbp. ckpl C pclk pin polarity 0 = rising edge 1 = falling edge hspl C hsync pin polarity 0 = active high 1 = active low vspl C vsync pin polarity 0 = active high 1 = active low depl C de pin polarity 0 = active high 1 = active low hbp[6:0] C horizontal back porch in pclk(used only if rgbif, sync=1, hbp > sdt ) hbp[6:0] horizontal back porch 7 ? h0 0 7 ? h1 1 x pclk 7 ? h2 2 x pclk : : : : 7 ? h7d 125 x pclk
LG4572B ver. 1.0. 4 lge confidential 178 7 ? ? vbp[7:0] : vertical back porch in line ( used only if rgbif, sync = 1 ) vbp[7:0] vertical back porch 8 ? ? ? : : : : 8 ? ? ? v s y n c h s y n c d c l k d b [ 2 3 : 0 ] h s y n c d c l k d b [ 1 7 : 0 ] 1 2 v b p : v e r t i c a l b a c k p o r c h p e r i o d h b p : h o r i z o n t a l b a c k p o r c h p e r i o d
LG4572B ver. 1.0. 4 lge confidential 179 6.2.40 b2h C panel characteristics setting b 2h panel characteristics setting dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 0 1 1 0 0 1 0 b2h 1 st parameter 1 #a #b x 0 0 lr selp 0 hrs [1:0] rev 10h 2 nd parameter 1 #a #b x vrs [7:0] d8h des criptio n write #a=1 #b= read #a= #b= 1 & insert dummy read lr C left & right control signals for gip circuits can be exchanged by using this register . if lr is high, then left and right signals are exchanged. but if low, then they remain as they are. selp C panel selec t 0 : l - type panel 1 : h - type panel hrs[1:0] h resolution in pixels 2 ? h0 480 pixels 2 ? h1 360 pixels (1~180 non - used, 181~1260 used, 1261~1440 non - used) 2 ? h2 320 pixels. (1~240 non - used, 241~1200 used, 1201~1440 non - use d) 2 ? h3 240 pixels. (1~360 non - used, 361~1080 used, 1081~1440 non - used) rev C 0 : normally black panel 1 : normally white panel vrs[7:0] C v resolution divided by 4. for example, if vrs is c8h (200 in decimal), vertical resoluti on is 864. vrs[7:0] vertical line 8 ? h0 0 line 8 ? h1 4 line 8 ? h2 8 line : : : :
LG4572B ver. 1.0. 4 lge confidential 180 8 ? ? ?
LG4572B ver. 1.0. 4 lge confidential 181 6.2.41 b3h C panel drive setting b 3h panel drive setting dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset comma nd 0 1 x 1 0 1 1 0 0 1 1 b3h 1 st parameter 1 #a #b x 0 0 0 0 0 0 dinv [1:0 ] 02h description write #a=1 #b= read #a= #b= 1 & insert dummy read dinv[1:0] C set the inversion mode. dinv[1:0] dot inversion mode 2 ? h0 c olumn inversion 2 ? h1 1 - dot 2 ? h2 2 - dot 2 ? h3 3 - dot 1 s t f r a m e 1 l i n e 2 l i n e 3 l i n e 4 l i n e 2 n d f r a m e 1 l i n e 2 l i n e 3 l i n e 4 l i n e + + - + - - - - + - + + + + - + - - + + - + - - + + - + - - - - + - + + - - + - + + - - + - + + 1 s t f r a m e 1 l i n e 2 l i n e 3 l i n e 4 l i n e + + - + - - + - - + - + + + - + - - + - - + - + 2 n d f r a m e 1 l i n e 2 l i n e 3 l i n e 4 l i n e + + - + - - + - - + - + + + - + - - + - - + - + 1 s t f r a m e 1 l i n e 2 l i n e 3 l i n e 4 l i n e + - - + + - - + + + - + + - - + + - - - 2 n d f r a m e 1 l i n e 2 l i n e 3 l i n e 4 l i n e - - + + + - + - - - - + - + + + + + - - + + - - - - + + 1 s t f r a m e 1 l i n e 2 l i n e 3 l i n e 4 l i n e + + - - + - - + 2 n d f r a m e 1 l i n e 2 l i n e 3 l i n e 4 l i n e + - - + - - + + - - - + + + + - + + + - - - - + - + + + + - - - + - - - - + + +
LG4572B ver. 1.0. 4 lge confidential 182 6.2.42 b4h C display mode control b 4h display mode control dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 0 1 1 0 1 0 0 b4h 1 st parameter 1 #a #b x 0 0 0 0 0 dith 0 0 04h description write #a= 1 #b= read #a= #b= 1 & insert dummy read dith C dither enable.(24bit ? 18bit) 1 : dither enable. 0 : dither disable.
LG4572B ver. 1.0. 4 lge confidential 183 6.2.43 b5h C display control 1 b 5h display control 1(source output control) (see below note) dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 0 1 1 0 1 0 1 b5h 1 st parameter 1 #a #b x sdt [7:0 ] 10h 2 nd parameter 1 #a #b x 0 shpn[6:0] 10h 3 rd parameter 1 #a #b x 0 engnd [6:0] 10h 4 th parameter 1 #a #b x shiz[7:0] 00h 5 th parameter 1 #a #b x 0 0 pts[1:0] 0 0 0 slt 20h description write #a=1 #b= read #a= #b= 1 & insert dummy read sdt[7:0] C s ource output delay , [1.. 255 ] pixel clocks dpi , mipi video sdt[7:0] s ource output delay time. 8 ? h00 setting disabled 8 ? h01 1 x pclk 8 ? h02 2 x pclk 8 ? hfd 253 x pclk 8 ? hfe 254 x pc lk 8 ? hff 255 x pclk i80, m68, mddi, mipi command sdt[7:0] s ource output delay time. 8 ? h00~8 ? h07 setting disabled 8?h08~8?h0f 1 x osc 8?h10~8?h17 2 x osc 8?h18~8?h1f 3 x osc 8?h20~8?h27 4 x osc 8?h28~8?h2f 5 x osc 8?h30~8?h37 6 x osc 8?h38~8?h3f 7 x osc
LG4572B ver. 1.0. 4 lge confidential 184 8?h40~8?h47 8 x osc 8?h48~8?h4f 9 x osc 8?h50~8?h57 10 x osc 8?h58~8?h5f 11 x osc 8?h60~8?h67 12 x osc 8?h68~8?h6f 13 x osc 8?h70~8?h77 14 x osc 8?h78~8?h7f 15 x osc 8?h80~8?h87 16 x osc 8?h88~8?h8f 17 x osc 8?h 90~8?h97 18 x osc 8?h98~8?h9f 19 x osc 8?ha0~8?ha7 20 x osc 8?ha8~8?haf 21 x osc 8?hb0~8?hb7 22 x osc 8?hb8~8?hbf 23 x osc 8?hc0~8?hc7 24 x osc 8?hc8~8?hcf 25 x osc 8?hd0~8?hd7 26 x osc 8?hd8~8?hdf 27 x osc 8?he0~8?he7 28 x osc 8?he8~ 8?hef 29 x osc 8?hf0~8?hf7 30 x osc 8?hf8~8?hff 31 x osc shpn[6:0], engnd[6:0] C dpi , mipi video shpn[6:0], engnd [6:0] set the charge sharing and gnd level period 7 ? ? ? : : 7 ? ? ? i80, m68, mddi, mipi command shpn[6:0], engnd [6:0] set the charge sharing and gnd level period
LG4572B ver. 1.0. 4 lge confidential 185 7 ? ? ?h08~8?h0f 1 x osc 7 ?h10~8?h17 2 x osc 7 ?h18~8?h1f 3 x osc 7 ?h20~8?h27 4 x osc 7 ?h28~8?h2f 5 x osc 7 ?h30~8?h37 6 x osc 7 ?h38~8?h3f 7 x osc 7 ?h40~8?h47 8 x osc 7 ?h48~8?h4f 9 x osc 7 ?h50~8?h57 10 x osc 7 ?h58~8?h5f 11 x osc 7 ?h60~8?h67 12 x osc 7 ?h68~8?h6f 13 x osc 7 ?h70~8?h77 14 x osc 7 ?h78~8?h7f 15 x osc shiz[7:0] C s ource output hi - z control through gdc, bdc . this parameter i s for engineering mode. if there were no speficific recommended values, the reset values should be used. dpi , mipi video shiz[7:0] s ource output hi - z control 8 ? ? ? 8 ? ? ? i80, m68, mddi, mipi command shiz[7:0] s ource output hi - z control 8 ? ? 8?h08~8?h0f 1 x osc 8?h10~8?h17 2 x osc 8?h18~8?h1f 3 x osc 8?hf0~8?hf7 30 x osc 8?hf8~8?hff 31 x osc
LG4572B ver. 1.0. 4 lge confidential 186 slt C spreaded source output enabling signal . this parameter is for engineering mode. if there were no speficific recommended values, the reset values should be used. 0 : 1 signal / 1 line 1 : 2 signal / 1 line pts[1:0] C set the source output in non - display drive peri od. pts[1:0] source output in non - display drive period 2 ? ? ? ? high - z note) shpn, engnd, and shiz don t have to be changed. their changes must be done with very care. so, they should be left just for engineering mode no t for the general ic users. this deletion doesn t mean not settable. they can be set but recommended not being changed! the default settings for them are highly recommended.
LG4572B ver. 1.0. 4 lge confidential 187 6.2.44 b6h C display control 2 b 6h display control 2 (gate output control) dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 0 1 1 1 0 1 0 b6h 1 st parameter 1 #a #b x 0 0 0 gswap fvst asg sdm fhm 01h 2 nd parameter 1 #a #b x clw [7:0] 18h 3 rd parameter 1 #a #b x 0 0 gto [5:0] 02h 4 th parameter 1 #a #b x gno[7:0] 40 h 5 th parameter 1 #a #b x fti [7:0] 10h 6 th parameter 1 #a #b x gpm[7:0] 00h
LG4572B ver. 1.0. 4 lge confidential 188 descriptio n write #a=1 #b= read #a= #b= 1 & insert dummy read in case of h - type panel (selp=1), asg and fhn are the related registers. according to asg, dual mode (asg=0) or single mode (asg=1) is selected. according to the fhn, non - overlap (fhn=0) or overlap (fhn=1) mode i s selected. the fti determines the delay time of starting signal (stpo or stpe) referring to hsync. and the clw determines the non - overlapping time between clks.. the following timing diagram and is for them. f t i s t p _ o ( g c l k 4 _ l ) c k _ o ( g c l k 2 _ l ) c k b _ o ( g c l k 3 _ l ) s t p _ e ( g c l k 4 - r ) c k _ e ( g c l k 2 _ r ) c k b _ e ( g c l k 3 _ r ) s n 1 2 3 4 5 6 c l w h s y n c v s y n c s d t
LG4572B ver. 1.0. 4 lge confidential 189 in case o f l - type panel (selp=0), fhn, sdm, , gswap, fvst , and fv (in 36h) are the related registers. according to the fhn, non - overlapping (fhn=0) or overlapping (fhn=1) mode is selected. according to the sdm, 4 - phase (sdm=0) or 8 - phase mode (sdm=1) is selected. f inally according to the fv, forward scan mode (fv=0) or reverse scan mode (fv=1) is selected. by using this reversed scan direction, flip vertical image can be gotten. but it should be noted that some l - type panels do not support this bi - directional scanni ng feature. non - overlapping control is done by using fti and clw registers. gvsts output delay timing referred to hsync can be set by fti register. and non - overlapping intervals between nearby gclks can be set by clw register. the setting choices are same as in the h - type panel case. dpi , mipi video clw[7:0] gclk non - overlap timing 8 ? ? ? 8 ? ? ? i80, m68, mddi, mipi comm and clw[7:0] gclk non - overlap timing 8?h00~8?h07 0 x osc 8?h08~8?h0f 1 x osc d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l v s t 1 g v s t 1 _ r v s t 2 g v s t 2 _ l v s t 3 g v s t 2 _ r v s t 4 g c l k 3 _ l c l k 5 g c l k 3 _ r c l k 6 1 2 3 1 2 4 3 g p w r 1 _ l g p w r 2 _ l g c l k 4 _ l c l k 7 g c l k 4 _ r c l k 8 g c l k 1 _ l c l k 1 g c l k 1 _ r c l k 2 g c l k 2 _ l c l k 3 g c l k 2 _ r c l k 4 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r f t i c l w s d t h s y n c f t i f t i f t i c l w c l w c l w c l w c l w c l w c l w s d t
LG4572B ver. 1.0. 4 lge confidential 190 8?h10~8?h17 2 x osc 8?h18~8?h1f 3 x osc 8?h20~8?h27 4 x osc 8?h28~8?h2f 5 x osc 8?h30~8?h37 6 x osc 8?h38~8?h3f 7 x osc 8?h40~8?h47 8 x osc 8?h48~8?h4f 9 x o sc 8?h50~8?h57 10 x osc 8?h58~8?h5f 11 x osc 8?h60~8?h67 12 x osc 8?h68~8?h6f 13 x osc 8?h70~8?h77 14 x osc 8?h78~8?h7f 15 x osc 8?h80~8?h87 16 x osc 8?h88~8?h8f 17 x osc 8?h90~8?h97 18 x osc 8?h98~8?h9f 19 x osc 8?ha0~8?ha7 20 x osc 8?ha8~8?haf 21 x osc 8?hb0~8?hb7 22 x osc 8?hb8~8?hbf 23 x osc 8?hc0~8?hc7 24 x osc 8?hc8~8?hcf 25 x osc 8?hd0~8?hd7 26 x osc 8?hd8~8?hdf 27 x osc 8?he0~8?he7 28 x osc 8?he8~8?hef 29 x osc 8?hf0~8?hf7 30 x osc 8?hf8~8?hff 31 x osc dpi , mipi video fti[7:0] gvst output delay 7 ? ? ? 7 ? ?
LG4572B ver. 1.0. 4 lge confidential 191 7 ? i80, m68, mddi, mipi command fti[7:0] gvst output delay 8?h00~8?h07 0 x osc 8?h08~8?h0f 1 x osc 8?h10~8?h17 2 x osc 8?h18~8?h1f 3 x osc 8?h20~8?h27 4 x osc 8?h28~8?h2f 5 x osc 8?h30~8?h37 6 x osc 8?h38~8?h3f 7 x osc 8?h40~8?h47 8 x osc 8?h48~8?h4f 9 x osc 8?h50~8?h57 10 x osc 8?h58~8?h5f 11 x osc 8?h60~8?h67 1 2 x osc 8?h68~8?h6f 13 x osc 8?h70~8?h77 14 x osc 8?h78~8?h7f 15 x osc 8?h80~8?h87 16 x osc 8?h88~8?h8f 17 x osc 8?h90~8?h97 18 x osc 8?h98~8?h9f 19 x osc 8?ha0~8?ha7 20 x osc 8?ha8~8?haf 21 x osc 8?hb0~8?hb7 22 x osc 8?hb8~ 8?hbf 23 x osc 8?hc0~8?hc7 24 x osc 8?hc8~8?hcf 25 x osc 8?hd0~8?hd7 26 x osc 8?hd8~8?hdf 27 x osc 8?he0~8?he7 28 x osc 8?he8~8?hef 29 x osc 8?hf0~8?hf7 30 x osc 8?hf8~8?hff 31 x osc
LG4572B ver. 1.0. 4 lge confidential 192 to get more stable panel electrical character istics, gno and gto registers are used only for the l - type panel. gto determines gpwrs toggle frequency and the gno determines the non - overlap timing between nearby gpwrs. the following timing diagram and the tables defines this. gto[5:0] gpwr toggle frequency 6 ? ? ? 6 ? ? ? dpi , mipi video gno[7:0] gpwr non - overlap timing 7 ? ? ? 7 ? ? ? g t o g p w r 1 _ l / r g p w r 2 _ l / r v s y n c g n o g n o g n o
LG4572B ver. 1.0. 4 lge confidential 193 i80, m68, mddi, mipi command gno[7:0] gpwr non - overlap timing 8?h00~8?h07 0 x osc 8?h08~8?h0f 1 x osc 8?h10~8?h17 2 x osc 8?h18~8?h1f 3 x osc 8?h20~8?h27 4 x osc 8?h28~8?h2f 5 x osc 8? he8~8?hef 29 x osc 8?hf0~8?hf7 30 x osc 8?hf8~8?hff 31 x osc for both h - and l - type panel cases, gate pulse modulation can be adopted to reduce source data sampling errors at the edge of gate falling by reducing the vgh and vgl voltage level dif ference when pixel data sampling. see the following functional diagram. the gate pulse modulated period (=gpm) can be controlled by using gpm register. dpi , mipi video gpm[7:0] d uration of gate pulse modulation 8 ? ? ? 8 ? ? ? i80, m68, mddi, mipi command gpm[7:0] d uration of gate pulse modulation 8?h00~8?h07 0 x osc g c l k 1 , 2 , 3 , 4 _ l , g c l k 1 , 2 , 3 , 4 _ r v g h d d v d h v g l g p m
LG4572B ver. 1.0. 4 lge confidential 194 8?h08~8?h0f 1 x osc 8?h10~8?h17 2 x osc 8?h18 ~8?h1f 3 x osc 8?h20~8?h27 4 x osc 8?h28~8?h2f 5 x osc 8?he8~8?hef 29 x osc 8?hf0~8?hf7 30 x osc 8?hf8~8?hff 31 x osc detailed waveforms with each cases are illustrated in the following figures. according to selp setting, either h - t ype panel (selp=1) or l - type panel (selp=0) case is selected.
LG4572B ver. 1.0. 4 lge confidential 195 h - type panel (selp = 1) the three following figures are for the h - type panel. they vary their waveforms according to the fhn and asg register settings. figure 83 . non - overlap, dual scan (fhn=0, asg=0) figure 84 . non - overlap, single scan (fhn= x , asg=1) s t p _ o ( g c l k 4 _ l ) c k _ o ( g c l k 2 _ l ) c k b _ o ( g c l k 3 _ l ) s t p _ e ( g c l k 4 _ r ) c k _ e ( g c l k 2 _ r ) c k b _ e ( g c l k 3 _ r ) s o u r c e o u t p u t 1 h s y n c v s y n c d e d b 1 7 - 0 8 6 4 1 8 6 3 2 3 4 5 6 7 8 2 3 4 5 6 7 8 6 2 8 6 3 8 6 4 s t p _ o / e ( g c l k 4 _ l / r ) c k _ o / e ( g c l k 2 _ l / r ) c k b _ o / e ( g c l k 3 _ l / r ) s o u r c e o u t p u t 1 h s y n c v s y n c d e d b 1 7 - 0 8 6 4 1 8 6 3 2 3 4 5 6 7 8 2 3 4 5 6 7 8 6 2 8 6 3 8 6 4
LG4572B ver. 1.0. 4 lge confidential 196 figure 85 . overlap, dual s can (fhn=0, asg=1) s t p _ o ( g c l k 4 _ l ) c k _ o ( g c l k 2 _ l ) c k b _ o ( g c l k 3 _ l ) s t p _ e ( g c l k 4 - r ) c k _ e ( g c l k 2 _ r ) c k b _ e ( g c l k 3 _ r ) s o u r c e o u t p u t 1 h s y n c v s y n c d e d b 1 7 - 0 8 6 4 1 8 6 3 2 3 4 5 6 7 8 2 3 4 5 6 7 8 6 2 8 6 3 8 6 4
LG4572B ver. 1.0. 4 lge confidential 197 l - type panel (selp = 0) the following figures are for the l - type panel. they vary their waveforms according to the fhn, sdm, fv and fvst register settings. when gswap register is set to high, gclk waveform swapping happens for each modes. figure 86 . non - overlap, 4 - phase, forward mode ( fhn=0, sdm=0, fv=0, fvst=0) n ote) gswap = 1 : gclk2_l(4_l) ? gclk1_l(3_l) swap, gclk1_r(3_r) ? gclk2_r(4_r) swap f igure 87 . non - overlap, 4 - phase, forward, advanced de mode ( fhn=0, sdm=0, fv=0, fvst=1) n ote) gswap = 1 : gclk2_l(4_l) ? gclk1_l(3_l) swap, gclk1_r(3_r) ? gclk2_r(4_r) swap d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 2 _ l g v s t 1 _ r g v s t 2 _ r g c l k 2 _ l g c l k 4 _ l 8 6 4 1 2 3 1 2 8 6 3 8 6 4 4 3 g p w r 1 _ l g p w r 2 _ l 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r g c l k 2 _ r g c l k 4 _ r g c l k 1 _ l g c l k 3 _ l f w _ l / r 1 g c l k 1 _ r g c l k 3 _ r b w _ l / r 0 8 6 4 1 2 3 1 2 8 6 3 8 6 4 4 3 5 6 7 8 4 5 6 7 d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 2 _ l g v s t 1 _ r g v s t 2 _ r g c l k 2 _ l g c l k 4 _ l g p w r 1 _ l g p w r 2 _ l g p w r 1 _ r g p w r 2 _ r g c l k 2 _ r g c l k 4 _ r g c l k 1 _ l g c l k 3 _ l f w _ l / r 1 g c l k 1 _ r g c l k 3 _ r b w _ l / r 0
LG4572B ver. 1.0. 4 lge confidential 198 figure 88 . overlap, 4 - phase, forward mode (fhn=1, sdm=0, fv=0, fvst=0) n ote) gswap = 1 : gclk2_l(4_l) ? gclk1_l(3_l) swap, gclk1_r(3_r) ? gclk2_r(4_r) swap figure 89 . overlap, 4 - phase, forward, advanced de mode ( fhn=1, sdm=0, fv=0, fvst=1) n ote) gswap = 1 : gclk2_l(4_l) ? gclk1_l(3_l) swap, gclk1_r(3_r) ? gclk2_r(4_r) swap d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 2 _ l g v s t 1 _ r g v s t 2 _ r g c l k 2 _ l g c l k 4 _ l 8 6 4 1 2 3 1 2 8 6 3 8 6 4 4 3 g p w r 1 _ l g p w r 2 _ l 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r g c l k 2 _ r g c l k 4 _ r g c l k 1 _ l g c l k 3 _ l f w _ l / r 1 g c l k 1 _ r g c l k 3 _ r b w _ l / r 0 8 6 4 1 2 3 1 2 8 6 3 8 6 4 4 3 5 6 7 8 4 5 6 7 d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 2 _ l g v s t 1 _ r g v s t 2 _ r g c l k 2 _ l g c l k 4 _ l g p w r 1 _ l g p w r 2 _ l g p w r 1 _ r g p w r 2 _ r g c l k 2 _ r g c l k 4 _ r g c l k 1 _ l g c l k 3 _ l f w _ l / r 1 g c l k 1 _ r g c l k 3 _ r b w _ l / r 0
LG4572B ver. 1.0. 4 lge confidential 199 figure 90 . non - overlap, 8 - phase, forward mode ( fhn=0, sdm=1, fv=0, fvst=0) n ote) gswap = 1 : gclk3_l/4_l ? gclk1_l/2_l swap, gclk3_r/4_r ? gclk1_r/2_r swap figure 91 . non - overlap, 8 - phase, forward, advanced de mode ( fhn=0, sdm=1, fv=0, fvst=1) n ote) gswap = 1 : gclk3_l/4_l ? gclk1_l /2_l swap, gclk3_r/4_r ? gclk1_r/2_r swap d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 1 _ r g v s t 2 _ l g v s t 2 _ r g c l k 3 _ l g c l k 3 _ r 4 8 0 1 2 3 1 2 4 7 9 4 8 0 4 3 g p w r 1 _ l g p w r 2 _ l g c l k 4 _ l g c l k 4 _ r g c l k 1 _ l g c l k 1 _ r g c l k 2 _ l g c l k 2 _ r 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r f w _ l / r 1 b w _ l / r 0 d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 1 _ r g v s t 2 _ l g v s t 2 _ r g c l k 3 _ l g c l k 3 _ r 4 8 0 1 2 3 1 2 4 7 9 4 8 0 4 3 g p w r 1 _ l g p w r 2 _ l g c l k 4 _ l g c l k 4 _ r g c l k 1 _ l g c l k 1 _ r g c l k 2 _ l g c l k 2 _ r 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r f w _ l / r 1 b w _ l / r 0
LG4572B ver. 1.0. 4 lge confidential 200 figure 92 . overlap, 8 - phase, forward mode ( fhn=1, sdm=1, fv=0, fvst=0) n ote) gswap = 1 : gclk3_l/4_l ? gclk1_l/2_l swap, gclk3_r/4_r ? gclk1_r/2_r swap figure 93 . overlap, 8 - phase, forward, advanced de mode ( fhn=1, sdm=1, fv=0, fvst=1) n ote) gswap = 1 : gclk3_l/4_l ? gclk1_l/2_l swap, gclk3_r/4_r ? gclk1_r/2_r swap d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 1 _ r g v s t 2 _ l g v s t 2 _ r g c l k 3 _ l g c l k 3 _ r 4 8 0 1 2 3 1 2 4 7 9 4 8 0 4 3 g p w r 1 _ l g p w r 2 _ l g c l k 4 _ l g c l k 4 _ r g c l k 1 _ l g c l k 1 _ r g c l k 2 _ l g c l k 2 _ r 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r f w _ l / r 1 b w _ l / r 0 d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 1 _ r g v s t 2 _ l g v s t 2 _ r g c l k 3 _ l g c l k 3 _ r 4 8 0 1 2 3 1 2 4 7 9 4 8 0 4 3 g p w r 1 _ l g p w r 2 _ l g c l k 4 _ l g c l k 4 _ r g c l k 1 _ l g c l k 1 _ r g c l k 2 _ l g c l k 2 _ r 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r f w _ l / r 1 b w _ l / r 0
LG4572B ver. 1.0. 4 lge confidential 201 figure 94 . non - overlap, 4 - phase, backward mode ( fhn=0, sdm=0, fv=1, fvst=0) n ote) gswap = 1 : gclk2_l(4_l) ? gclk1_l(3_l) swap, gclk1_r(3_r) ? gclk2_r(4_r) swap figure 95 . non - overlap, 4 - p hase, backward, advanced de mode ( fhn=0, sdm=0, fv=1, fvst=1) n ote) gswap = 1 : gclk2_l(4_l) ? gclk1_l(3_l) swap, gclk1_r(3_r) ? gclk2_r(4_r) swap d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 2 _ l g v s t 1 _ r g v s t 2 _ r g c l k 2 _ l g c l k 4 _ l 8 6 4 1 2 3 1 2 8 6 3 8 6 4 4 3 g p w r 1 _ l g p w r 2 _ l 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r g c l k 2 _ r g c l k 4 _ r g c l k 1 _ l g c l k 3 _ l f w _ l / r 0 g c l k 1 _ r g c l k 3 _ r b w _ l / r 1 8 6 4 1 2 3 1 2 8 6 3 8 6 4 4 3 5 6 7 8 4 5 6 7 d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 2 _ l g v s t 1 _ r g v s t 2 _ r g c l k 2 _ l g c l k 4 _ l g p w r 1 _ l g p w r 2 _ l g p w r 1 _ r g p w r 2 _ r g c l k 2 _ r g c l k 4 _ r g c l k 1 _ l g c l k 3 _ l f w _ l / r 0 g c l k 1 _ r g c l k 3 _ r b w _ l / r 1
LG4572B ver. 1.0. 4 lge confidential 202 figure 96 . overlap, 4 - phase, backward mode ( fhn=1, sdm =0, fv=1, fvst=0) n ote) gswap = 1 : gclk2_l(4_l) ? gclk1_l(3_l) swap, gclk1_r(3_r) ? gclk2_r(4_r) swap figure 97 . overlap, 4 - phase, backward, advanced de mode ( fhn=1, sdm=0, fv=1, fvst=1) n ote) gswap = 1 : gclk2_l(4_l) ? gclk1_l(3_l) swap, gclk1_r(3_r) ? gclk2_r(4_r) swap d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 2 _ l g v s t 1 _ r g v s t 2 _ r g c l k 2 _ l g c l k 4 _ l 8 6 4 1 2 3 1 2 8 6 3 8 6 4 4 3 g p w r 1 _ l g p w r 2 _ l 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r g c l k 2 _ r g c l k 4 _ r g c l k 1 _ l g c l k 3 _ l f w _ l / r 0 g c l k 1 _ r g c l k 3 _ r b w _ l / r 1 8 6 4 1 2 3 1 2 8 6 3 8 6 4 4 3 5 6 7 8 4 5 6 7 d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 2 _ l g v s t 1 _ r g v s t 2 _ r g c l k 2 _ l g c l k 4 _ l g p w r 1 _ l g p w r 2 _ l g p w r 1 _ r g p w r 2 _ r g c l k 2 _ r g c l k 4 _ r g c l k 1 _ l g c l k 3 _ l f w _ l / r 0 g c l k 1 _ r g c l k 3 _ r b w _ l / r 1
LG4572B ver. 1.0. 4 lge confidential 203 figure 98 . non - overlap, 8 - phase, backward mode ( fhn=0, sdm=1, fv=1, fvst=0) n ote) gswap = 1 : gclk3_l/4_l ? gclk1_l/2_l swap, gclk 3_r/4_r ? gclk1_r/2_r swap figure 99 . non - overlap, 8 - phase, backward, advanced de mode ( fhn=0, sdm=1, fv=1, fvst=1) n ote) gswap = 1 : gclk3_l/4_l ? gclk1_l/2_l swap, gclk3_r/4_r ? gclk1_r/2_r swap d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 1 _ r g v s t 2 _ l g v s t 2 _ r g c l k 3 _ l g c l k 3 _ r 4 8 0 1 2 3 1 2 4 7 9 4 8 0 4 3 g p w r 1 _ l g p w r 2 _ l g c l k 4 _ l g c l k 4 _ r g c l k 1 _ l g c l k 1 _ r g c l k 2 _ l g c l k 2 _ r 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r f w _ l / r 0 b w _ l / r 1 d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 1 _ r g v s t 2 _ l g v s t 2 _ r g c l k 3 _ l g c l k 3 _ r 4 8 0 1 2 3 1 2 4 7 9 4 8 0 4 3 g p w r 1 _ l g p w r 2 _ l g c l k 4 _ l g c l k 4 _ r g c l k 1 _ l g c l k 1 _ r g c l k 2 _ l g c l k 2 _ r 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r f w _ l / r 0 b w _ l / r 1
LG4572B ver. 1.0. 4 lge confidential 204 figure 100 . overlap, 8 - phase, backward mode ( fhn=1, sdm=1, fv=1, fvst=0) n ote) gswap = 1 : gclk3_l/4_l ? gclk1_l/2_l swap, gclk3_r/4_r ? gclk1_r/2_r swap figure 101 . overlap, 8 - phase, backward, advanced de mode ( fhn=1, sdm=1, fv=1, fvst=1) n ote) gswap = 1 : gclk3_l/4_l ? gclk1_l/2_l swap, gclk3_r/4_r ? gclk1_r/2_r swap d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 1 _ r g v s t 2 _ l g v s t 2 _ r g c l k 3 _ l g c l k 3 _ r 4 8 0 1 2 3 1 2 4 7 9 4 8 0 4 3 g p w r 1 _ l g p w r 2 _ l g c l k 4 _ l g c l k 4 _ r g c l k 1 _ l g c l k 1 _ r g c l k 2 _ l g c l k 2 _ r 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r f w _ l / r 0 b w _ l / r 1 d e ( i n t e r n a l d e ) d b 1 7 - 0 s n g v s t 1 _ l g v s t 1 _ r g v s t 2 _ l g v s t 2 _ r g c l k 3 _ l g c l k 3 _ r 4 8 0 1 2 3 1 2 4 7 9 4 8 0 4 3 g p w r 1 _ l g p w r 2 _ l g c l k 4 _ l g c l k 4 _ r g c l k 1 _ l g c l k 1 _ r g c l k 2 _ l g c l k 2 _ r 5 6 7 8 4 5 6 7 g p w r 1 _ r g p w r 2 _ r f w _ l / r 0 b w _ l / r 1
LG4572B ver. 1.0. 4 lge confidential 205 6.2.45 b7h C display control 3 b7h display control 3 dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 0 1 1 0 1 1 1 b7h 1 st parameter 1 #a #b x rtn[7:0] 46h 2 nd parameter 1 #a #b x fp[7:0] 06h 3 rd parameter 1 #a #b x bp[7:0] 0ch 4 th parameter 1 #a #b x div[1:0] 00h 5 th parameter 1 #a #b x tei[2:0] 00h descri ption write #a=1 #b= read #a= #b= 1 & insert dummy read rtn[7:0] C sets 1h (line) period. this setting is enabled while the lg 4572b ?s display operation is synchronized with internal clock. rtn[7:0] should be greater than or equal to 70 (= 46 h). rtn[7:0] clock per l ine 8 ? h00 C 8 ? h45 setting disabled 8 ? h46 70 clocks 8 ? h47 71 clocks 8 ? h48 72 clocks : : 8 ? hfc 252 clocks 8 ? hfe 254 clocks 8 ? hff 255 clocks bp[7:0], fp[7:0] C these parameters define the retrace period (i.e. front and back porches) which a ppears before and after the display area. fp[7:0] bits define number of front porch lines while bp [7:0] bits define number of back porch lines.
LG4572B ver. 1.0. 4 lge confidential 206 description bp[7:0] / fp[7:0] number of lines for the back/front porches 8 ? ? ? ? ? ? ? ? div[1:0] C ? div[1:0] division ratio internal operation clock unit 2 ? ? ? ? tei[2:0] C tei[2:0] te output interval in frames 3 ? ? ? ? ?
LG4572B ver. 1.0. 4 lge confidential 207 6.2.46 c0h C internal oscillator setting c0h internal oscillat or setting dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 0 0 0 0 0 0 c0h 1 st parameter 1 #a #b x 0 0 0 0 0 osc sync ext osc osc 01h 2 nd parameter 1 #a #b x 0 0 0 frs [4:0] 00h description write #a=1 #b= read #a= #b= 1 & insert dummy read lg 4572b supports oscsync mode, where one ic ? s internally generated oscillation frequency can be shared to others through osc3 pin. oscsync C osc sync mode control oscsync description 1 ? h0 ocs sync mode enable disabled 1 ? h1 o cs sync mode disable enabled lg 4572b supports external osc mode, where external r and c components are used for determining oscillation frequency in case higher frequencies than 6.28mhz are needed. in external osc mode, internal oscillator cannot operate any more. extosc C use the external osc extosc description 1 ? h0 internal osc 1 ? h1 external osc osc C osc control hatlosc description 1 ? h 0 halt osc 1 ? h 1 normal operation frs[4:0] C internal o scillator frequency control . lg 4572b supports vari ous oscillation frequencies as bellows . frs[4:0] f requency [mhz] frs[4:0] f requency [mhz] 5 ? h00 0.23 5?h 10 3.37 5 ? h01 0.47 5?h 11 3.56 5 ? h02 0.56 5?h 12 3.63 5 ? h03 0.81 5?h 13 3.79 5 ? h04 0.90 5?h 14 3.92
LG4572B ver. 1.0. 4 lge confidential 208 5 ? 5?h1 ? 5 ?h1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
LG4572B ver. 1.0. 4 lge confidential 209 6.2.47 c1h C power control 1 c1h power control 1(power state selection) dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 0 0 0 0 0 1 c1h 1 st parameter 1 #a #b x 0 0 0 0 dte 0 stb dstb 02h description write #a=1 #b= read #a= #b= 1 & insert dummy read dstb C when dstb = 1, the lgd 4572b enters the deep standby mode. in deep standby mode, the internal logic power supply is turned off to reduce power consumption. in the deep standby mode, data stored in the instr uctions are not retained. rewrite them after the deep standby mode is exited. dstb description 1 ? h0 normal operation 1 ? h1 deep standby mode. stb C when stb = 1, the lg 4572b enters the standby mode. in standby mode, the display operation complete ly halts, and the internal operation, including internal rc oscillation and reception of external clock pulses, completely halts. only instructions to release the lg 4572b from the standby mode (stb = 0) and to start oscillators are accepted during the st andby mode. to set the standby mode, follow the sequence of standby mode setting. stb description 1 ? h0 normal operation 1 ? h1 standby mode dte C manual gate output enable dte description 1 ? h0 gate output disable 1 ? h1 gate output enable
LG4572B ver. 1.0. 4 lge confidential 210 6.2.48 c2h C power control 2 c2h power control 2(manual step - up circuit enable) dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 0 0 0 0 1 0 c2h 1 st parameter 1 #a #b x 0 0 lvgl vdl vcl vgl vgh vdh 00h description write #a=1 #b= read #a= #b= 1 & insert dummy read vdh C enable the operation switching regulator to generate ddvdh. vdh description 1 ? h0 ddvdh off 1 ? h1 ddvdh on vdl C enable the operation to generate ddvdl. vdl description 1 ? h0 ddvdl off 1 ? h1 dd vdl on vcl C enable the operation to generate vcl. vcl description 1 ? h0 vcl off 1 ? h1 vcl on vgl C enable the operation to generate vgl. vgl description 1 ? h0 vgl off 1 ? h1 vgl on vgh C enable the operation to generate vgh. vgh descr iption 1 ? h0 vgh off 1 ? h1 vgh on
LG4572B ver. 1.0. 4 lge confidential 211 lvgl C lvgl description 1 ? ?
LG4572B ver. 1.0. 4 lge confidential 212 6.2.49 c3h C power control 3 c3h power control 3(step - up circuit control) dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 0 0 0 0 1 1 c3h 1 st parameter 1 #a #b x 0 0 0 0 0 stmode[2:0] 00h 2 nd parameter 1 #a #b x 0 0 0 0 0 dc1[2:0] 04h 3 rd parameter 1 #a #b x 0 0 0 0 0 dc2[2:0] 03h 4 th parameter 1 #a #b x 0 0 0 0 0 dc3[2:0] 03h 5 th parameter 1 #a #b x 0 0 0 0 0 dcpfm[2:0] 04h descriptio n write #a=1 #b= read #a= #b= 1 & insert dummy read stmode [2:0] C these bits set the step - up auto power generation modes. 1~3 are for h - type panel and 5~7 are for l - type panel. 0 and 4 are for manual power generation settings. stmode [2:0] ddvdh circuit ddvdl circuit power setting 3 ? h0 manual manual manual 3 ? h1 external ddvdh step - up3 auto 3 ? h2 pfm boosting step - up3 auto 3 ? h3 pfm boosting diode inverting auto 3 ? h4 manual manual manual 3 ? h5 external ddvdh step - up3 auto 3 ? h6 pfm boosting step - up3 a uto 3 ? h7 pfm boosting diode inverting auto dc1[2:0] C these bits set the step - up clock frequency of the step - up circuit 2 . dc1[2:0] step - up circuit 2 : step - up frequency (fdcdc2) osc = 1 osc = 0 3 ? h0 fosc/8 fpclk / 64 3 ? h1 fosc/16 fpclk / 128 3 ? h2 fosc/32 fpclk / 256 3 ? h3 fosc/64 fpclk / 512 3 ? h4 fosc/128 fpclk / 1024
LG4572B ver. 1.0. 4 lge confidential 213 3 ? ? ? dc2[2:0] C dc2[2:0] step - up circuit 3 : step - up frequency (fdcdc3) osc = 1 osc = 0 3 ? ? ? ? ? ? ? ? dc3[2:0] C dc3[2:0] step - up circuit 4 : step - up frequency (fdcdc4) osc = 1 osc = 0 3 ? ? ? ? ? ? ? ? dcpfm[2:0] C dcpfm[2:0] pfm circuit : step - up frequency (fdcdc_pfm) osc = 1 osc = 0 3 ? ? ? ? ? ?
LG4572B ver. 1.0. 4 lge confidential 214 3 ? ?
LG4572B ver. 1.0. 4 lge confidential 215 restriction e n _ v g h e n _ v g l p o w e r o n s t m o d e [ 2 : 0 ] = 2 h 1 f r a m e e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e g a t e _ o n 1 f r a m e d i s p l a y o n e n _ l v g l s o u r c e r e g o n o s c o n e n _ v g h e n _ v g l p o w e r o f f s t m o d e [ 2 : 0 ] = 2 h e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e g a t e _ o n d i s p l a y o n e n _ l v g l s o u r c e r e g o n o s c o n 1 f r a m e 1 f r a m e 1 f r a m e e n _ v g h e n _ v g l p o w e r o n s t m o d e [ 2 : 0 ] = 3 h 1 f r a m e e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e g a t e _ o n 1 f r a m e d i s p l a y o n e n _ l v g l s o u r c e r e g o n o s c o n e n _ v g h e n _ v g l p o w e r o f f s t m o d e [ 2 : 0 ] = 3 h e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e g a t e _ o n d i s p l a y o n e n _ l v g l s o u r c e r e g o n o s c o n 1 f r a m e 1 f r a m e 1 f r a m e e n _ v g h e n _ v g l p o w e r o n s t m o d e [ 2 : 0 ] = 1 h 1 f r a m e e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e g a t e _ o n 1 f r a m e d i s p l a y o n e n _ l v g l s o u r c e r e g o n o s c o n e n _ v g h e n _ v g l p o w e r o f f s t m o d e [ 2 : 0 ] = 1 h e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e g a t e _ o n d i s p l a y o n e n _ l v g l s o u r c e r e g o n o s c o n 1 f r a m e 1 f r a m e 1 f r a m e
LG4572B ver. 1.0. 4 lge confidential 216 restriction e n _ v g h e n _ v g l p o w e r o n s t m o d e [ 2 : 0 ] = 5 h 1 f r a m e e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e g a t e _ o n 1 f r a m e d i s p l a y o n s o u r c e r e g o n o s c o n e n _ v g h e n _ v g l p o w e r o f f s t m o d e [ 2 : 0 ] = 5 h e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e g a t e _ o n d i s p l a y o n s o u r c e r e g o n o s c o n 1 f r a m e 1 f r a m e 1 f r a m e e n _ v g h e n _ v g l p o w e r o n s t m o d e [ 2 : 0 ] = 6 h 1 f r a m e e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e g a t e _ o n 1 f r a m e d i s p l a y o n s o u r c e r e g o n o s c o n e n _ v g h e n _ v g l p o w e r o f f s t m o d e [ 2 : 0 ] = 6 h e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e g a t e _ o n d i s p l a y o n s o u r c e r e g o n o s c o n 1 f r a m e 1 f r a m e 1 f r a m e e n _ v g h e n _ v g l p o w e r o n s t m o d e [ 2 : 0 ] = 7 h 1 f r a m e e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e 1 f r a m e g a t e _ o n 1 f r a m e d i s p l a y o n s o u r c e r e g o n o s c o n e n _ v g h e n _ v g l p o w e r o f f s t m o d e [ 2 : 0 ] = 7 h e n _ p f m e n _ v c l e n _ v d l s l p 1 f r a m e g a t e _ o n d i s p l a y o n s o u r c e r e g o n o s c o n 1 f r a m e 1 f r a m e 1 f r a m e
LG4572B ver. 1.0. 4 lge confidential 217 6.2.50 c4h C power control 4 c4h power control 4(regulator control) dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 0 0 0 1 0 0 c4h 1 st parameter 1 #a #b x 0 0 opb bmb 0 bdc [2:0] 00h 2 nd parameter 1 #a #b x 0 gdc[2:0] 0 ap[2:0] 00h 3 rd parameter 1 #a #b x 0 0 0 vrh1[4:0 ] 00h 4 th parameter 1 #a #b x 0 0 0 vrh2[4:0 ] 00h 5th parameter 1 #a #b x 0 0 0 regpd 0 bt[2:0] 05h 6 th parameter 1 #a #b x 0 vbs [2:0] vrefs [3:0] 0bh description write #a=1 #b= read #a= #b= 1 & insert dummy read opb C normal & buffered bias selection opb channel amp bias 1 ? h0 buffered bias 1 ? h1 normal bias bmb C bias line current adjustment. bmb line current 1 ? h0 2 1 ? h1 1 bdc [ 2 :0] C channel a m p quiesc ent current adjustment . bdc[2:0] channel amp bias 3 ? h0 channel amp halt 3 ? h1 0.5 3 ? h2 1 3 ? h3 1.5 3 ? h4 2 3 ? h5 2.5 3 ? h6 3 3 ? h7 3.5
LG4572B ver. 1.0. 4 lge confidential 218 gdc [2:0] C gdc[2:0] gray amp bias 3 ? ? ? ? ? ? ? ? ap [2:0] C ap[2:0] bias of regulator 3 ? ? ? ? ? ? ? ? vrh1 [ 4 :0] C vrh1[4:0] vreg1out level vrh1[4:0] vreg1out level 5 ? 5?h10 ? 5?h11 ? 5?h12 ? 5?h13 ? 5?h14 ? 5?h15 ? 5?h16 ? 5?h17 ? 5?h18 ? 5?h19 ? 5?h1a ? 5?h1b ? 5?h1c ? 5?h1d ? 5?h1e ? 5?h1f
LG4572B ver. 1.0. 4 lge confidential 219 vrh2 [ 4 :0] C vrh2[4:0] vreg2out level vrh2[4:0] vreg2out level 5 ? 5?h10 ? 5?h11 ? 5?h12 ? 5?h13 ? 5?h14 ? 5?h15 ? 5?h16 ? ?h17 ? 5?h18 ? 5?h19 ? 5?h1a ? 5?h1b ? 5?h1c ? 5?h1d ? 5?h1e ? 5?h1f regpd C bt [2:0] C bt[2:0] ddvdh ddvdl vgh vgl capacitor connection pins 3?h0 C C 3?h1 C C 3?h2 C C 3?h3 C C 3?h4 C C 3?h5 C C 3?h6 C C 3?h7 C C
LG4572B ver. 1.0. 4 lge confidential 220 notes: 1. the step - up rate from the vci level is shown in the bracket [ ] in the above table. 2. when using the ddvdh, ddvdl, vcl, vgh and vgl voltage lev els, connect a capacitor to each capacitor connection pin. set the following voltages within the limits: ddvdh = max 6 v, vcl = min C C vbs [2:0] C vbs[2:0] vbias 3 ? ? ? ? ? ? ? ? vrefs [ 3 :0] C vrefs [ 3 :0] ddvdh voltage vrefs [ 3 :0] ddvdh voltage 4 ? ? ? 4 ? ? 4 ? ? 4 ? ? 4 ? ? 4 ? ? 4 ? ? 4 ?
LG4572B ver. 1.0. 4 lge confidential 221 6.2.51 c5h C power control 5 c5h power control 5( vcom control) dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 0 0 0 1 0 1 c5h 1 st parameter 1 #a #b x 0 vcm [6:0] 00h description write #a=1 #b= read #a= #b= 1 & insert dummy read note : set the vcoml voltage from vre g2out level to 0v vcm[6:0] C sets the vcom level . vcm[6:0] specifies the voltage by vreg 2 out x n, where n can change from 0. 1 to 1 as shown in below table . to halt internal setting and adjust vcom through vcomr pad , set vcm[6:0] = 1111111 . then, vcom level follows vcomr level. vcm [6:0] vcom vcm [6:0] vcom vcm [6:0] vcom vcm [6:0] vcom 7?h00 halt(vcom=gnd) 7?h 2 0 vreg2out x 0.779 7?h 4 0 vreg2out x 0.550 7?h 6 0 vreg2out x 0.321 7?h01 vreg2out x 1 7?h 2 1 vreg2out x 0.771 7?h 4 1 vreg2out x 0.543 7?h 6 1 vr eg2out x 0.314 7?h02 vreg2out x 0.993 7? h2 2 vreg2out x 0.764 7? h4 2 vreg2out x 0.536 7? h6 2 vreg2out x 0.307 7?h03 vreg2out x 0.986 7?h 2 3 vreg2out x 0.757 7?h 4 3 vreg2out x 0.529 7?h 6 3 vreg2out x 0.3 7?h04 vreg2out x 0.979 7?h 24 vreg2out x 0.750 7?h 44 v reg2out x 0.521 7?h 64 vreg2out x 0.293 7?h05 vreg2out x 0.971 7?h 2 5 vreg2out x 0.743 7?h 4 5 vreg2out x 0.514 7?h 6 5 vreg2out x 0.286 7?h06 vreg2out x 0.964 7?h 2 6 vreg2out x 0.736 7?h 4 6 vreg2out x 0.507 7?h 6 6 vreg2out x 0.279 7?h07 vreg2out x 0.957 7?h 2 7 vreg2out x 0.729 7?h 4 7 vreg2out x 0.5 7?h 6 7 vreg2out x 0.271 7?h08 vreg2out x 0.950 7?h 2 8 vreg2out x 0.721 7?h 4 8 vreg2out x 0.493 7?h 6 8 vreg2out x 0.264 7?h09 vreg2out x 0.943 7?h 2 9 vreg2out x 0.714 7?h 4 9 vreg2out x 0.486 7?h 6 9 vreg2out x 0.257 7?h 0a vreg2out x 0.936 7? h2 a vreg2out x 0.707 7? h4 a vreg2out x 0.479 7? h6 a vreg2out x 0.250 7?h0b vreg2out x 0.929 7?h 2 b vreg2out x 0.7 7?h 4 b vreg2out x 0.471 7?h 6 b vreg2out x 0.243 7?h0c vreg2out x 0.921 7?h 2 c vreg2out x 0.693 7?h 4 c vreg2out x 0.464 7?h 6 c vreg2out x 0.236 7?h0d vreg2out x 0.914 7?h 2 d vreg2out x 0.686 7?h 4 d vreg2out x 0.457 7?h 6 d vreg2out x 0.229 7?h0e vreg2out x 0.907 7?h 2 e vreg2out x 0.679 7?h 4 e vreg2out x 0.450 7?h 6 e vreg2out x 0.221 7?h0f vreg2out x 0.9 7?h 2 f vreg2out x 0.671 7?h 4 f vreg2out x 0.443 7?h 6 f vreg2out x 0.214 7?h10 vreg2out x 0.893 7?h 3 0 vreg2out x 0.664 7?h 5 0 vreg2out x 0.436 7?h 7 0 vreg2out x 0.207 7?h11 vreg2out x 0.886 7?h 3 1 vreg2out x 0.657 7?h 5 1 vreg2out x 0.429 7?h 7 1 vreg2out x 0.2 7?h12 vreg2out x 0.879 7? h 3 2 vreg2out x 0.650 7?h 5 2 vreg2out x 0.421 7?h 7 2 vreg2out x 0.193 7?h13 vreg2out x 0.871 7?h 3 3 vreg2out x 0.643 7?h 5 3 vreg2out x 0.414 7?h 7 3 vreg2out x 0.186 7?h14 vreg2out x 0.864 7?h 3 4 vreg2out x 0.636 7?h 5 4 vreg2out x 0.407 7?h 7 4 vreg2out x 0.179 7?h15 vreg2out x 0.857 7?h 3 5 vreg2out x 0.629 7?h 5 5 vreg2out x 0.4 7?h 7 5 vreg2out x 0.171 7?h16 vreg2out x 0.850 7?h 3 6 vreg2out x 0.621 7?h 5 6 vreg2out x 0.393 7?h 7 6 vreg2out x 0.164 7?h17 vreg2out x 0.843 7?h 3 7 vreg2out x 0.614 7?h 5 7 vreg2out x 0.386 7?h 7 7 vreg2out x 0.157 7?h18 vreg2out x 0.836 7?h 3 8 vreg2out x 0.607 7?h 5 8 vreg2out x 0.379 7?h 7 8 vreg2out x 0.150 7?h19 vreg2out x 0.829 7?h 3 9 vreg2out x 0.6 7?h 5 9 vreg2out x 0.371 7?h 7 9 vreg2out x 0.143 7?h0a vreg2out x 0.821 7?h 3 a vreg2out x 0.593 7?h 5 a vreg2out x 0.364 7?h 7 a vreg2out x 0.136
LG4572B ver. 1.0. 4 lge confidential 222 7?h0b vreg2out x 0.814 7?h 3 b vreg2out x 0.586 7?h 5 b vreg2out x 0.357 7?h 7 b vreg2out x 0.129 7?h0c vreg2out x 0.807 7?h 3 c vreg2out x 0.579 7?h 5 c vreg2out x 0.350 7?h 7 c vreg2out x 0.121 7?h0d vreg2out x 0. 8 7?h 3 d vreg2out x 0.571 7?h 5 d vreg2out x 0.343 7?h 7 d vreg2out x 0.114 7?h0e vreg2out x 0.793 7?h 3 e vreg2out x 0.564 7?h 5 e vreg2out x 0.336 7?h 7 e vreg2out x 0.107 7?h0f vreg2out x 0.786 7?h 3 f vreg2out x 0.557 7?h 5 f vreg2out x 0.329 7?h 7 f vcomr
LG4572B ver. 1.0. 4 lge confidential 223 6.2.52 c6h C p ower control 6 c6h power control 6(vdd regulator control) dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 0 0 0 1 1 0 c6h 1 st parameter 1 #a #b x 0 ri[2:0] 0 rv [2:0] 23h 2 nd parameter 1 #a #b x 0 reset [2:0] 0 rcont [2:0] 40h description write #a=1 #b= read #a= #b= 1 & insert dummy read ri[2:0] C these bits control the bias current of internal logic regulator. ri[2:0] logic regulator bias current 3 ? h0 x 0.2 3 ? h1 x 1 3 ? h2 x 2 3 ? h3 x 3 3 ? h4 x 3 3 ? h5 x 4 3 ? h6 x 5 3 ? h7 x 6 rv[2:0] C these bits control the output voltage of internal logic regulator. rv[2:0] vdd voltage 3 ? h0 vci x 0.60 3 ? h1 vci x 0.575 3 ? h2 vci x 0.55 3 ? h3 vci x 0.525 3 ? h4 vci x 0.50 3 ? h5 vci x 0.474 3 ? h6 vci x 0.45 3 ? h7 vci x 0.425
LG4572B ver. 1.0. 4 lge confidential 224 reset [ 2 :0] C reset[2:0] main bias current 3 ? ? ? ? ? ? ? ? rcont[2:0] C rcont[2:0 ] main bias voltage 3 ? ? ? ? ? ? ? ?
LG4572B ver. 1.0. 4 lge confidential 225 6.2.53 c7h C offset ca ncelling control c7h source channel amp offset cancelling control (see note below) dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 rese t command 0 1 x 1 1 0 0 0 1 1 1 c7h 1 st parameter 1 #a #b x 0 0 0 0 0 0 0 ofcen 00h 2 nd parameter 1 #a #b x ofctsw[7: 0] 30h 3 rd parameter 1 #a #b x ofctd2 [3:0] ofctd1 [3:0] 10h description write #a=1 #b= read #a= #b= 1 & insert dummy read ofcen C offset cancelling enable/disable ofcen offset cancelling 1 ? h0 offset canceling disable 1 ? h1 offset cancel ing enable ofctsw [ 6 :0] C set the offset sampling period. ofctsw [ 7 :0] offset sampling period 7 ? h00 0 7 ? h01 1 x pclk 7 ? h02 2 x pclk 7 ? h03 3 x pclk : : : : 7 ? hfc 252 x pclk 7 ? hfd 253 x pclk 7 ? hfe 254 x pclk 7 ? hff 255 x pclk ofctd1 [ 3 :0] C set the delay of the offset sampling start ofctd1[3:0] delay of the offset sampling start ofctd1[3:0] delay of the offset sampling start 4 ? h0 0 4 ? h8 8 x pclk 4 ? h1 1 x pclk 4 ? h9 9 x pclk 4 ? h2 2 x pclk 4 ? ha 10 x pclk 4 ? h3 3 x pclk 4 ? hb 11 x pclk 4 ? h4 4 x pclk 4 ? hc 12 x pclk 4 ? h5 5 x pclk 4 ? hd 13 x pclk 4 ? h6 6 x pclk 4 ? he 14 x pclk 4 ? h7 7 x pclk 4 ? hf 15 x pclk
LG4572B ver. 1.0. 4 lge confidential 226 ofctd2 [ 3 :0] C ofctd2[3:0] ofctd2[3:0] 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? note) the c 7h register is recommended to use the default settings.
LG4572B ver. 1.0. 4 lge confidential 227 6.2.54 c8h C backlight control c8h backlight control dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 0 0 1 0 0 0 c8h 1 st parameter 1 #a #b x cdsp[3:0] cdmp[3:0] 82h 2 nd parameter 1 #a #b x pwmp 0 0 0 0 0 fpwm[1:0] 01h description write #a=1 #b= read #a= #b= 1 & insert dummy read cdsp[3:0] C dimming control of still image. cdsp[3:0] dimming control step cdsp[3:0] dimming control step 4 ? h0 0 4 ? h8 8 4 ? h1 1 4 ? h9 9 4 ? h2 2 4 ? ha 10 4 ? h3 3 4 ? hb 11 4 ? h4 4 4 ? hc 12 4 ? h5 5 4 ? hd 13 4 ? h6 6 4 ? he 14 4 ? h7 7 4 ? hf 15 cdmp[3:0] C dimming control of moving image . cdmp[3:0] dimming control step cdmp[3:0] dimming control step 4 ? h0 0 4 ? h8 8 4 ? h1 1 4 ? h9 9 4 ? h2 2 4 ? ha 10 4 ? h3 3 4 ? hb 11 4 ? h4 4 4 ? hc 12 4 ? h5 5 4 ? hd 13 4 ? h6 6 4 ? he 14 4 ? h7 7 4 ? hf 15 pwmp C pwm output polarity. pwmp pwmp polarity 0 active high 1 active low fpwm[1:0] C pwm frequency setting. fpwm[1:0] pwm frequency 2 ? h0 frame frequency x 2 2 ? h1 frame frequency x 4 2 ? h2 frame frequency x 8 2 ? h3 frame frequency x 16
LG4572B ver. 1.0. 4 lge confidential 228 6.2.55 d0h C positive gamma curve for red mnemonic rgammap type read/write parameters no. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reset 1 - pkp1[2:0] - pkp0[2:0] 00h 2 - pkp3[2:0] - pkp2[2:0] 00h 3 - pkp5[2:0] - pkp4[2:0] 00h 4 - prp1[2:0] - prp0[2:0 ] 00h 5 - - - vrp0[4:0] 00h 6 - - - vrp1[4:0] 00h 7 - pfp1[2:0] - pfp0[2:0] 00h 8 - pfp3[2:0] - pfp2[2:0] 00h 9 - - - - - pmp[2:0] 00h description pkp 0 - 5 [2:0] C gamma fine - adjustment register for positive polarity prp 0 - 1 [2:0] C gamma gradient - adj ustment register for positive polarity vrp 0 - 1 [3:0] C gamma amplitude - adjustment register for positive polarity pfp 0 - 3 [2:0] C gamma fine adjustment register bits for positive polarity pmp[2:0] C gamma fine adjustment register bits for positive polarity for details, see g amma correction function section .
LG4572B ver. 1.0. 4 lge confidential 229 6.2.56 d1h C negative gamma curve for red mnemonic rgamma n type read/write parameters no. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reset 1 - pk n 1[2:0] - pkn0 [2:0] 00h 2 - pkn3 [2:0] - pkn2 [2:0] 00h 3 - pkn5 [2:0] - pkn4 [2:0] 00 h 4 - prn1 [2:0] - prn0 [2:0] 00h 5 - - - vrn0 [4:0] 00h 6 - - - vrn1 [4:0] 00h 7 - pfn1 [2:0] - pfn0 [2:0] 00h 8 - pfn3 [2:0] - pfn2 [2:0] 00h 9 - - - - - pmn [2:0] 00h description pk n0 - 5 [2:0] C gamma fine - adjustment register for negative polarity pr n0 - 1 [2:0] C gamma gradient - adjustment register for negative polarity vr n0 - 1 [3:0] C gamma amplitude - adjustment register for negative polarity pf n0 - 3 [2:0] C gamma fine adjustment register bits for negative polarity pm n [2:0] C gamma fine adjustment register bits for negative polarity for details, see g amma correction function section .
LG4572B ver. 1.0. 4 lge confidential 230 6.2.57 d2h C positive gamma curve for green mnemonic ggammap type read/write parameters no. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reset 1 - pkp1[2:0] - pkp0[2:0] 00h 2 - pkp3[2:0] - pkp2[2:0] 00h 3 - pkp5[2:0] - pkp4[2:0] 00h 4 - prp1[2:0] - prp0[2:0] 00h 5 - - - vrp0[4:0] 00h 6 - - - vrp1[4:0] 00h 7 - pfp1[2:0] - pfp0[2:0] 00h 8 - pfp3[2:0] - pfp2[2:0] 00h 9 - - - - - pmp[2:0] 00h description pkp 0 - 5 [2:0] C gamma fine - adjustment registe r for positive polarity prp 0 - 1 [2:0] C gamma gradient - adjustment register for positive polarity vrp 0 - 1 [3:0] C gamma amplitude - adjustment register for positive polarity pfp 0 - 3 [2:0] C gamma fine adjustment register bits for positive polarity pmp[2:0] C gamma fine adjustment register bits for positive polarity for details, see g amma correction function section .
LG4572B ver. 1.0. 4 lge confidential 231 6.2.58 d3h C negative gamma curve for green mnemonic ggamman type read/write parameters no. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reset 1 - pkn1 [2:0] - pkn0 [2:0] 00h 2 - pkn3 [2:0] - pkn2 [2:0] 00h 3 - pkn5 [2:0] - pkn4 [2:0] 00h 4 - prn1 [2:0] - prn0 [2:0] 00h 5 - - - vrn0 [4:0] 00h 6 - - - vrn1 [4:0] 00h 7 - pfn1 [2:0] - pfn0 [2:0] 00h 8 - pfn3 [2:0] - pfn2 [2:0] 00h 9 - - - - - pmn [2:0] 00h description pk n0 - 5 [2:0] C gamma fine - adjustment register for negative polarity pr n0 - 1 [2:0] C gamma gradient - adjustment register for negative polarity vr n0 - 1 [3:0] C gamma amplitude - adjustment register for negative polarity pf n0 - 3 [2:0] C gamma fine adjustment register bits for negati ve polarity pm n [2:0] C gamma fine adjustment register bits for negative polarity for details, see g amma correction function section .
LG4572B ver. 1.0. 4 lge confidential 232 6.2.59 d4h C positive gamma curve for blue mnemonic bgammap type read/write parameters no. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reset 1 - pkp1[2:0] - pkp0[2:0] 00h 2 - pkp3[2:0] - pkp2[2:0] 00h 3 - pkp5[2:0] - pkp4[2:0] 00h 4 - prp1[2:0] - prp0[2:0] 00h 5 - - - vrp0[4:0] 00h 6 - - - vrp1[4:0] 00h 7 - pfp1[2:0] - pfp0[2:0] 00h 8 - pfp3[2:0] - pfp2[2:0] 00h 9 - - - - - pmp[2:0] 00h description pkp 0 - 5 [2:0] C gamma fine - adjustment register for positive polarity prp 0 - 1 [2:0] C gamma gradient - adjustment register for positive polarity vrp 0 - 1 [3:0] C gamma amplitude - adjustment register for positive polarity pfp 0 - 3 [2:0] C gamma fine adjustm ent register bits for positive polarity pmp[2:0] C gamma fine adjustment register bits for positive polarity for details, see g amma correction function section .
LG4572B ver. 1.0. 4 lge confidential 233 6.2.60 d5 h C negative gamma curve for blue mnemonic bgamman type read/write parameters no. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reset 1 - pkn1 [2:0] - pkn0 [2:0] 00h 2 - pk n p3[2:0] - pkn2 [2:0] 00h 3 - pkn5 [2:0] - pkn4 [2:0] 00h 4 - pr n 1[2:0] - prn0 [2:0] 00h 5 - - - vrn0 [4:0] 00h 6 - - - vrn1 [4:0] 00h 7 - pfn1 [2:0] - pfn0 [2:0] 00h 8 - pfn3 [2:0] - pfn2 [2:0] 00h 9 - - - - - pmn [2:0] 00h description pk n0 - 5 [2:0] C gamma fine - adjustment register for negative polarity pr n0 - 1 [2:0] C gamma gradient - adjustment register for negative polarity vr n0 - 1 [3:0] C gamma amplitude - adjustment register for negative polarity pf n 0 - 3 [2:0] C gamma fine adjustment register bits for negative polarity pm n [2:0] C gamma fine adjustment register bits for negative polarity for details, see g amma correction function section .
LG4572B ver. 1.0. 4 lge confidential 234 6.2.61 e0h C mddi control e0h mddi control dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 1 0 0 0 0 0 e0h 1 st parameter 1 #a #b x 0 ref[2:0] 0 0 0 lpm 30h 2 nd parameter 1 #a #b x 0 0 0 0 0 txemp[1:0] txen 03h 3 rd parameter 1 #a #b x 0 0 data0_reset[5:0] 00h 4 th parameter 1 #a #b x 0 0 data1_r eset[5:0] 04h 5 th parameter 1 #a #b x 0 0 data1_offset[5:0] 02h 6 th parameter 1 #a #b x 0 0 stb_reset[5:0] 00h description write #a=1 #b= read #a= #b= 1 & insert dummy read ref[2:0] C common mode voltage level control for tx in mddi ref[2:0] tx driver common mode voltage level 2 ? h0 vci x 0.33 2 ? h1 vci x 0.32 2 ? h2 vci x 0.31 2 ? h3 vci x 0.30 2 ? h4 vci x 0.29 2 ? h5 vci x 0.28 2 ? h6 vci x 0.27 2 ? h7 vci x 0.26 lpm C l ow power mode enable 0 : normal mode 1 : low power mode (enabled) txem p[1:0] C tx driver output overdrive txemp[1:0] tx driver output overdrive 2 ? h0 normal operation mode (2 ? ) 2 ? h1 overdrive mode (2.5 ? ) 2 ? h2 overdrive mode (2.5 ? ) 2 ? h3 overdrive mode (3 ? )
LG4572B ver. 1.0. 4 lge confidential 235 txen C data0_reset[5:0] C data1_reset[5:0] C data1_offset[5: 0] C stb_reset[5:0] C
LG4572B ver. 1.0. 4 lge confidential 236 6.2.62 e1h C frame memory control e1h frame memory control dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 rese t command 0 1 x 1 1 1 0 0 0 0 1 e1h 1 st parameter 1 #a #b x 0 0 0 0 0 0 dcmr[1:0] 02h 2 nd parameter 1 #a #b x 0 0 0 0 0 0 0 ecc byp 00h 3 rd parameter 1 #a #b x 0 0 0 0 0 0 ss[2:0] 02h 4 th parameter 1 #a #b x 0 0 0 opt[4:0] 00h description write #a=1 #b= read #a= #b= 1 & insert dummy read eccb y p C memory ecc bypass 0 : ecc enabled 1 : ecc bypass (test mode only) ss[2:0] C memory lcd clock frequency selection ss[2:0] memory lcd clock frequency (mhz) max min 3 ? h0 s etting disabled s etting dis abled 3 ? h1 s etting disabled s etting disabled 3 ? h2 2.556 4.666 3 ? h3 2.4 4.32 3 ? h4 1.92 3.456 3 ? h5 1.5 2.592 3 ? h6 s etting disabled s etting disabled 3 ? h7 s etting disabled s etting disabled dcmr[1:0] C sets the memory refresh clock d ivision ra tio of the internal clock frequency . dcmr[1:0] memory refresh clock frequency 2 ? h0 fosc/48 2 ? h1 fosc/64 2 ? h2 fosc/96 2 ? h3 fosc/128 opt [4:0] C programmable options. static mode only.
LG4572B ver. 1.0. 4 lge confidential 237 6.2.63 e2h C eeprom read control e2h eeprom read control dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 1 0 0 0 1 0 e2h 1 st parameter 1 #a #b x rfclk[3:0] 0 0 0 eep rom 00h descriptio n write #a=1 #b= read #a= #b= 1 & insert dummy read rfclk[3:0] C i2c clock frequency for eeprom reading access . it can be set from 0 to 12 and the other settings are not allowed. the equation of rscl frequency for register reading from eeprom is as follows. rsclk = (oscillator frequency) / (16 C rfclk)
LG4572B ver. 1.0. 4 lge confidential 238 6.2.64 f0h C test register 1 f0h test register 1 dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 1 1 0 0 0 0 f0h 1 st parameter 1 #a #b x hiz 0 0 0 0 0 tpol[1:0] 00h description write #a=1 #b= read #a= #b= 1 & insert dummy read tpol[1:0] C lcd polarity inversion control . ( test mode ) hiz C vlout3 and vlout4 outputs to hi - z .
LG4572B ver. 1.0. 4 lge confidential 239 6.2.65 f1h C test register 2 f1h memory bist control dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 1 1 0 0 0 1 f1h 1 st parameter 1 #a #b x balg[2:0] 00h 2 nd parameter 1 #a #b x edthr[7:0] 80h 3 rd parameter 1 #a #b x mdrt[7:0] 00h description write #a=1 #b= read #a= #b= 1 & insert dummy read balg[2:0] C bist algorithm ed thr[7:0] C error detect threshold(test only) mdrt[7:0] C memory data retention time
LG4572B ver. 1.0. 4 lge confidential 240 6.2.66 f8h C otp 1 f8h otp programming control dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 1 1 1 0 0 0 f8h 1 st parameter 1 #a #b x ptm [1:0] 0 0 prd pwe vpp pprog 00h 2 nd parameter 1 #a #b x aprg 0 0 0 0 0 pa[1:0] 00h 3 rd parameter 1 #a #b x pdin [7:0] 00h description write #a=1 #b= read #a= #b= 1 & insert dummy read pprog C p rogram mode enable . vpp : power switch control for the vpp pin of the embedded otp. when vpp = 1 , the internal vpp is set to 7. 7 5v; otherwise it is set to vdd . this vpp register parameter is differen t from vpp in pad. pwe C write enable . prd C pin for power - on rest . ptm[1:0] C pins for enabling test mode . pa[1:0] C address input. this selects one of four banks of the eprom . pa[1:0] write data input write opt cell 2 ?h0 pdin[6:0] cell[6:0] 2 ?h1 pdin[6:0] cell[14:8] 2 ?h2 pdin[6:0] cell[22:16] 2 ?h3 pdin[6:0] cell[30:24] aprg C select the metho d of write operation aprg w rite o peration 1 ?h0 w rite address is pa . 1 ?h0 w rite address is auto select address . pdin [ 7 :0] C data input.
LG4572B ver. 1.0. 4 lge confidential 241 6.2.67 f 9 h C otp 2 f9h otp read control dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 1 1 1 0 0 1 f9h 1 st parameter 1 #a #b x vcmsel [1:0] 0 0 0 0 ra[1:0] description write #a=1 #b= read #a= #b= 1 & insert dummy read ra[ 1:0] C read address input. this selects one of four banks of the eprom . ra[1:0] read data input read opt cell 2 ?h0 pdout [6:0] cell[6:0] 2 ?h1 pdout [6:0] cell[14:8] 2 ?h2 pdout [6:0] cell[22:16] 2 ?h3 pdout[6:0] cell[30:24] vcmsel[1:0] C s ets vcom level from either the register c5 h or the eprom . vcmsel[1:0] vcom level adjustment 2 ?h0 vcm[6:0] of the register c5h 2 ?h1 eprom data at first if eprom has data. otherwise, vcm[6:0] of the register c5h 2 ?h2 eprom data selected by ra[1:0] 2 ?h 3 eprom data selected by ra[1:0]
LG4572B ver. 1.0. 4 lge confidential 242 6.2.68 f a h C otp 3 fah read otp data dcx rdx wrx d [23:8] d7 d6 d5 d4 d3 d2 d1 d0 reset command 0 1 x 1 1 1 1 1 0 1 0 fah 1 st parameter 1 #a #b x pdout [7:0] - 2 nd parameter 1 #a #b x pdout [15:8] - 3 rd parameter 1 #a #b x pdout [23:16] - 4 th parameter 1 #a #b x pdout [31:24] - descriptio n write #a=1 #b= read #a= #b= 1 & insert dummy read pdout[31:0] C eeprom read data
LG4572B ver. 1.0. 4 lge confidential 243 7 electrical characteristics 7.1 absolute maximum ratings table 17 . absolute maximum ratings . item symbol unit min max notes power supply voltage (1) vdd v - 0.3 2.6 1 p ower supply voltage (2) vcc, iovcc ? gnd v - 0.3 4.5 1, 2 power supply voltage (3) vci ? gnd v - 0.3 4.5 1, 2 power supply voltage (4) ddvdh v - 0.3 8.0 1, 3, 4 power supply voltage (5) vgnd ? vcl v - 0.3 4.5 1 power supply voltage (6) vgh ? ag nd v - 0.3 15 1, 5 power supply voltage (7) agnd ? vgl (or lvgl) v - 0.3 14.5 1, 6 input voltage vt v - 0.3 iovcc+0.3 1 operating temperature topr c - 40 85 1, 7 storage temperature tstg c - 55 125 1 notes: 1. if used beyond the absolute maximum rating s, the lsi may permanently be damaged. it is strongly recommended to use the lsi at a condition within the electrical characteristics for normal operation. exposure to a condition not within the electrical characteristics may affect device reliability. 2. make sure (high) vci gnd (low). (high) iovcc gnd (low). (high) vcc gnd (low). 3. m ake sure (high) ddvdh agnd (low). 4. make sure (high) ddvdh vci (low). 5. make sure (high) vgh gnd (low). 6. make sure (high) gnd vgl (or lvgl) (low). 7. the dc/ac chara cteristics of die and wafer products is guaranteed at 85 c. 8. make sure (high) vgh ? vgl ( or lvgl) < 29.5 v .
LG4572B ver. 1.0. 4 lge confidential 244 7.2 power supply specifications table 18 . power supply specifications no. item lg 4572b 1 tft source lines 1440 pins (480 x rg b) 2 gip control signals fw_l, bw_l, gpwr1_l, gpwr2_l, gclk4_l, gclk3_l, gclk2_l, gclk1_l, gvst1_l, gvst2_l, fw_r, bw_r, gpwr1_r, gpwr2_r, gclk4_r, gclk3_r, gclk2_r, gclk1_r, gvst1_r, gvst2_r, 3 input voltages iovcc 1.65 to 3.30 v vcc 2.60 to 3.30 v vci 2.60 to 3.30 v 4 internal logic voltages vdd 1. 4 0 to 1. 7 0 v 5 internal step - up circuits ddvdh vci x (1.47 to 2.45) ddvdl - ddvdh vgh ddvdh x 2, ddvdh x 2 + vci, ddvdh x 3 vgl - (ddvdh x 2), - (ddvdh x 2 + vci), - (ddvdh x 3) lvgl vgl - vci vcl vci x - 1
LG4572B ver. 1.0. 4 lge confidential 245 7.3 dc characteristics table 19 . dc characteristics item symbol unit test condition min typ max notes input high voltage v ih v iovcc = 1.65~3.3 0.8 * iovcc - iovcc input low voltage v il v iovcc = 1.65~3.3 - 0.3 - 0.2 * i ovcc output high voltage (1) (db17 - 0, sdo) v oh1 v iovcc = 1.65~3.3 ioh = 0.1ma 0.8 * iovcc - - output low voltage ( 1 ) (db17 - 0, sdo) v ol1 v iovcc = 1.65~3.3 iol = 0.1ma - - 0.2 * iovcc i/o leakage current i li a vin = 0~iovcc - 1 - 1 current consumption during s tandby mode : (iovcc - gnd) i st _iovcc a iovcc = 2.8v ta = 25 c - 1.4 10 current consumption during s tandby mode : ( vcc - gnd) + ( vci - gnd) i st _vcc + i st _vci a vcc = vci = 2.8v ta = 25 c 100 150 1, mddi 20 30 rgb 20 30 mipi 20 30 cpu current consumption during deep s tandby mode : ( vcc - gnd) + ( vci - gnd) + (iovcc C gnd) i d st a iovcc = vcc = vci = 2.8v ta = 25 c 0 2 m ddi, rgb, mipi, cpu notes: 1. the standby current in mddi interface case should be update later. t h is typical value is based on the simulation results temporarily just for a reference.
LG4572B ver. 1.0. 4 lge confidential 246 7.4 ac characteristics 7.4.1 mipi hs receiver characteristics table 20 . dc characteristics of mipi hs receiver parameter description min nom max units notes v cmrx(dc) common - mode voltage hs receive mode 70 330 mv v idth differential input high threshold 100 mv v idtl differential input low threshold - 100 mv v ihhs single - ended input high voltage 460 mv v ilhs single - ended input low voltage - 40 m v v term - en single - ended threshold for hs termination enable 450 mv z id differential input impedance 80 100 125 ohm the differential input high and low threshold voltages of the hs receiver are denoted by v idth and v idtl , respectively. v ilhs and v i hhs are the single - ended, input low and input high voltages, respectively. v cmrx(dc) is the differential input common - mode voltage.
LG4572B ver. 1.0. 4 lge confidential 247 figure 102 . signaling voltage levels. table 21 . ac characteristics of m ipi hs receiver parameter description min nom max units notes ui inst data rate (ui instantaneous) 3.0 12.5 ns t setup data to clock setup time 0.15 ui inst 1 t shold clock to data hold time 0.15 ui inst 1 t skew data to clock skew - 0.15 0.15 ui inst notes : 1. total setup and hold window for receiver of 0.3*ui inst
LG4572B ver. 1.0. 4 lge confidential 248 figure 103 . ac timing waveform for hs mode mipi o peration 7.4.2 mipi lp receiver characteristic s table 22 . dc cha racteristics of mipi lp receiver parameter description min nom max unit notes v ih logic 1 input voltage 880 mv v il logic 0 input voltage 550 mv v il - ulps logic 0 input voltage, ulp state 300 mv v hyst input hysteresis 25 mv table 23 . ac characteristics of mipi lp receiver parameter description min nom max unit notes e spike input pulse rejection 300 vp - s 1, 2 t min - rx minimum pulse width response 20 ns 3 v int peak interference amplitude 200 mv f int interferen ce frequency 450 mhz notes: 1. time - voltage integration of a spike above v il when being in lp - 0 state or below v ih when being in lp - 1 state. 2. an impulse less than this will not change the receiver state. 3 . an input pulse greater than this shall togg le the output. t s e t u p d a t a p d a t a n t h o l d 0 . 5 u i i n s t + t s k e w c l k p c l k n 1 u i i n s t
LG4572B ver. 1.0. 4 lge confidential 249 figure 104 . ac timing waveform for lp mode mipi o peration 7.4.3 mipi lp transmitter characteristics table 24 . dc characteristics of mipi lp transmitter . parameter description min nom max unit notes v oh thevenin output high level 1.1 1.2 1.3 v v ol thevenin output low level - 50 50 mv z ol p output impedance of lp transmitter 110 ohm 1 notes: 1 . though no maximum value for z olp is specified, the lp transmitter output impedance shall ensure the t rlp /t flp specification is met. v ol is the thevenin output, low - level voltage in the lp transmit mode. this is the voltage at an unloaded pad pin in the low - level state. v oh is the thevenin output, high - level voltage in t he high - level state, when the pad pin is not loaded. table 25 . ac characteristics of mipi lp transmitter parameter description min nom max units notes t rlp /t flp 15% - 85% rise time and fall time 25 ns 1 t reot thevenin output lo w level 35 ns 1, 5, 6 t lp - pulse - tx pulse width of the lp exclusive - or clock first lp exclusive - or clock pulse after stop state or last pulse before stop state 40 ns 4 v i h v i l i n p u t o u t p u t 2 * t l p x 2 * t l p x t m i n - r x t m i n - r x e s p i k e e s p i k e
LG4572B ver. 1.0. 4 lge confidential 250 all other pulses 20 ns 4 t lp - per - tx period of the lp exclusive - or clock 90 ns ? v/ ? t sr slew rate @ c load = 0pf 30 500 mv/ns 1, 2, 3 slew rate @ c load = 5pf 30 200 mv/ns 1, 2, 3 slew rate @ c load = 20pf 30 150 mv/ns 1, 2, 3 slew rate @ c load = 70pf 30 100 mv/ns 1, 2, 3 c load load capacitance 0 70 pf 1 notes: 1. c load includes the low - frequency equivalent transmission line capacitance. the capacitance of tx and rx are assumed to always be <10pf. the distributed line capacitance can be up to 50pf for a transmission line with 2ns delay. 2. when the output voltage is between 15% and below 85% of the fully settled lp signal levels. 3. measured as average across any 50 mv segment of the output signal transition. 4. this parameter value can be lower then t lpx due to differences in rise vs. fall signal slopes an d trip levels and mismatches between dp and dn lp transmitters. 5. the rise - time of t reot starts from the hs common - level at the moment the differential amplitude drops below 70mv, due to stopping the differential drive. 6. with an additional load capacit ance c cm between 0 - 60pf on the termination center tap at rx side of the lane the times t rlp and t flp are the 15% - 85% rise and fall times, respectively, of the output signal voltage, when the lp transmitter is driving a capacitive load c load . the 15% - 85% l evels are relative to the fully settled v oh and v ol voltages. the slew rate v/ t sr is the derivative of the lp transmitter output signal voltage over time. the slew rate specification shall be met for the 15% - 85% range while driving a capacitive load, c l oad . figure 105 . slew rate of lp tx vs. c load
LG4572B ver. 1.0. 4 lge confidential 251 7.4.4 mddi transmitter characteristics the requirements of transmitter are listed in the t able below . the load capacitance of the measurement probe must be less than 10 pf between each sig nal and the client ground, and less than 5 pf across each signal of a differential pair. no load must be present on the differential pairs other than the parasitic capacitance of the measurement probe. table 26 . electrical specific ation of mddi transmitter in lg 4572b parameter description mddi 1.2 unit min typ max v output - range - int allowable client driver output voltage range with respect to client ground (internal mode) 0.6 1.1 v i od+ driver differential output high current corresponding to logic - one level (while driving the equivalent of the pull - up and pull - down circuits that exist at the host and client) 1.5 2 2.5 ma i od - driver differential output high current corresponding to logic - zero level (while driving the equival ent of the pull - up and pull - down circuits that exist at the host and client) - 2.5 - 2 - 1.5 ma z out - client minimum differential output impedance of the mddi_data drivers in the client device 1 kohm t rise - fall rise and fall time (between 20% and 80% amplitude) of driver output, measured in differential mode 200 note 1 psec t skew - pair skew between positive and negative outputs of the same differential pair 50 psec t b - drvr jitter, bit boundary to minimum output level 0.15t bit note 1 : the maximum rise and fall time is either 35% of the interval to transmit one bit on one differential pair or 100nsec, whichever smaller.
LG4572B ver. 1.0. 4 lge confidential 252 figure 106 . transmitter eye diagram (r term is defined in the receiver specification) figure 107 . skew between positive and negative outputs 7.4.5 mddi receiver characteristics the requirements are listed in th e table below . the load capacitance of the measurement probe must be less than 10 pf between each signal and the host ground, and less than 5 pf across each signal of a differential pair. no load must be present on the differential pairs other than the par asitic capacitance of the measurement probe. t b t b i t - t b t b i t i o d + ( m a x ) x r t e r m ( m a x ) 8 0 % x i o d + ( m i n ) x r t e r m ( m i n ) 8 0 % x i o d - ( m a x ) x r t e r m ( m i n ) i o d - ( m i n ) x r t e r m ( m a x ) 0 . 0 d i f f e r e n t i a l a m p l i t u d e ( v o l t s ) t i m e 0 . 0 0 . 0 d i f f e r e n t i a l s i g n a l w a v e f o r m s t i m e t s k e w - p a i r t s k e w - p a i r 0 . 0
LG4572B ver. 1.0. 4 lge confidential 253 table 27 . electrical specification of mddi receiver in lg 4572b parameter description mddi 1.2 unit min typ max v it+ receiver differential input high threshold voltage. above this di fferential voltage the input signal must be interpreted as a logic - one level 0 50 mv v it - receiver differential input low threshold voltage. above this differential voltage the input signal must be interpreted as a logic - zero level - 50 0 mv v it+ receiv er differential input high threshold voltage ( offset for hibernation wake - up). above this differential voltage the input signal must be interpreted as a logic - one level 100 125 mv v it - receiver differential input low threshold voltage ( offset for hiberna tion wake - up). above this differential voltage the input signal must be interpreted as a logic - zero level 75 100 mv r term parallel termination resistance value 98 100 102 o hm v input - range allowable receiver input voltage range with respect to client gro und. 0.5 1.2 v t diff - skew peak delay skew between one differential pair and any other differential pair 0.45t bit t a jitter, bit boundary to center crossing 0.1t bit t b - rcvr jitter, bit boundary to minimum input level 0.15t bit t bit receiver max imum operation speed (1/t bit = bps) 2.5 ns
LG4572B ver. 1.0. 4 lge confidential 254 figure 108 . receiver eye diagram figure 109 . peak delay skew between differential pairs 7.4.6 interconne ct network requirement for mddi interconnect network characteristics for mddi are described as follows. table 28 . interconnect network characteristics for mddi parameter description mddi 1.2 unit t a t b t b i t - t b t b i t - t a t b i t i o d + ( m a x ) x r t e r m ( m a x ) v i t + ( m a x ) i o d - ( m i n ) x r t e r m ( m a x ) 0 . 0 d i f f e r e n t i a l a m p l i t u d e ( v o l t s ) t i m e 0 . 0 v i t - ( m i n ) 0 . 0 d i f f e r e n t i a l s i g n a l w a v e f o r m s t i m e t d i f f - s k e w d a t a m t d i f f - s k e w d a t a n
LG4572B ver. 1.0. 4 lge confidential 255 parameter description mddi 1.2 unit min typ max z 0 transmission l ine differential impedance of each differential pair 80 100 120 ohm t prop propagation time of a differential signal through the interconnect network 0 1.5 nsec t skew - pair skew between positive and negative output of the same differential pair(intra - pair skew) 50 psec t diff - skew peak delay skew between one differential pair and any other differential pair(inter - pair skew) 100 psec r dc - signal series resistance of each wire in a differential pair of the mddi_stb+/ - , or mddi_data0+/ - through mddi_data# +/ - signals on the interconnect network, includes resistance of conductors and emi filtering components 0 4 ohm v dc - pwr voltage drop in host_gnd in the cable between host and receiver 0 110 mv c diff capacitance between the two signals of a differential pair in the matched line in the internal network 7.5 pf
LG4572B ver. 1.0. 4 lge confidential 256 figure 110 . propagation time through interconnect network figure 111 . interconnect network skew between positive and negative outputs i n t e r c o n n e c t n e t w o r k + a - + b - 0 . 0 d i f f e r e n t i a l s i g n a l w a v e f o r m s t i m e t p r o p b a t p r o p 0 . 0 d i f f e r e n t i a l s i g n a l w a v e f o r m s t i m e t s k e w - p a i r t s k e w - p a i r 0 . 0
LG4572B ver. 1.0. 4 lge confidential 257 figure 112 . interconnect network p eak delay skew between differential pairs 0 . 0 d i f f e r e n t i a l s i g n a l w a v e f o r m s t i m e t d i f f - s k e w d a t a m t d i f f - s k e w d a t a n
LG4572B ver. 1.0. 4 lge confidential 258 7.4.7 serial peripheral interface characteristics table 29 . (condition: iovcc = 1.65 to 3.30v, vcc = 2.60 to 3.30v) item symbol unit min typ max serial clock cycle time write (received) tscyc ns 20 - - read (transmitted) 100 - - serial clock high level pulse width write (received) tsch ns 10 - - read (transmitted) 50 - - serial clock low level pulse width write (received) tscl ns 10 - - read (transmitted) 50 - - serial clock rise/fall time tscr, tscf ns - - 20 chip select setup time tcsu ns 20 - - chip select hold time tch ns 10 - - s erial input data setup time tsisu ns 5 - - serial input data hold time tsih ns 10 - - serial output data setup time tsod ns 80 - 150 serial output data hold time tsoh ns - - 80 figure 113 . serial p eripheral interface operation 7.4.8 reset timing characteristics table 30 . ( condition: iovcc = 1.65 to 3.30v, vcc = 2.60 to 3.30v) item symbol unit min typ max reset low level width tres ms 1 - - reset rise time trres s - - 10 wrb_e_sck tcsu sdi csb tsch tsisu input data sdo o utput data input data o utput data start: s endl p vil vil vih vil vih vil vil vih vil vih tscl tscr tscf tch vil vih vil vih tsih vol voh vol voh tsod tsoh
LG4572B ver. 1.0. 4 lge confidential 259 figure 114 . reset operation 7.4.9 rgb interface timing characteristics table 31 . (24/18/16 - bit i/f, iovcc = 1.65 to 3.30v, vcc = 2.60 to 3.30v) item symbol unit min typ max vsync/hsync s etup time tsyncs ns 10 - - vsync/hsync hold time tsynch ns 10 - - de setup time tens ns 10 - - de hold time tenh ns 10 - - pclk low level pulse width pwdl ns 20 - - pclk high level pulse width pwdh ns 20 - - pclk cycle time tcycd ns 40 - - data setup time tpds ns 10 - - date hold time tpdh ns 10 - - pclk, vsync, hsync, de rise/fall time trgbr, trgbf ns - - 13 figure 115 . rgb interface 7.4.10 68 - system bus interface timing characteristics (18/16 - bit bus) table 32 . 68 - system bus interface timing (condition: iovcc = 1.65 to 3.30v, vcc = 2.60 to 3.30v) item symbol unit min. typ. max. de db23 - 0 pclk vsync hsync write data vih tens tenh pw dl pw dh tpds tpd h tcycd v il vih v il vih v il vih v il v il vih vih v il v il vih vih v il vih v il vih v il vih v il tsyncs vih v il vih v il trgbf trgbr trgbf trgbf tsynch trgbf trg br vih v il vih v il reset* tres vil vih vil trres
LG4572B ver. 1.0. 4 lge confidential 260 bus cycle time write tcyce ns 40 - - read tcyce ns 300 - - write low level pulse width read low level pulse width write pwel ns 20 - - read pwel ns 150 - - write high level pulse width read high level pulse width write pweh ns 20 - - read pweh ns 150 - - w rite/read rise/fall time ter, tef ns - 10 s etup time write (rs, rw to e) tase ns 0 - - read (rs, rw to e) 10 - - address hold time tahe ns 5 - - write data setup time tdswe ns 10 - - write data hold time the ns 5 - - read data delay time tddre ns - - 100 read data hold time tdhre ns 5 - - figure 116 . 68 - system bus interface operation 7.4.11 80 - system bus interface timing characteristics (18/16 - bit bus) table 33 . 80 - system bus interface timing (condition: iovcc = 1.65 to 3.30v, vcc = 2.60 to 3.30v) item symbol unit min. typ. max. bus cycle time write tcycw ns 40 - - read tcycw ns 300 - - write low level pulse width read low level pulse width write pwlw ns 20 - - read pwlr ns 150 - - v i h v i h v i h v i h v i h v i h v i l v i h v i h v o h 1 v o h 1 v i l v i l v i l v i l v i l v i l v i l v i l v o l 1 v o l 1 t a s e t a h e p w e h p w e l t c y c e t e r t e f t d s w e t h e t d d r e t d h r e r s r w c s b e s e e n o t e 2 ) d b 0 ~ d b 1 7 s e e n o t e 2 ) d b 0 ~ d b 1 7 s e e n o t e 1 ) n o t e 1 ) p w e w i s d e f i n e d b y t h e o v e r l a p p e r i o d w h e n c s b i s l o w a n d e i s h i g h . n o t e 2 ) u n u s e d d b p i n s m u s t b e f i x e d a t i o v c c o r g n d . w r i t e d a t a r e a d d a t a
LG4572B ver. 1.0. 4 lge confidential 261 write high level pulse width read high le vel pulse width write pwhw ns 20 - - read pwhr ns 150 - - w rite/read rise/fall time twrr,twrf ns - 10 s etup time write (rs, rw to e) tas ns 0 - - read (rs, rw to e) 10 - - address hold time tah ns 5 - - write data setup time tdsw ns 10 - - wr ite data hold time th ns 5 - - read data delay time tddr ns - - 100 read data hold time tdhr ns 5 - - figure 117 . 80 - system bus interface operation v i h v i h v i h v i h v i h v i h v i h v i h v i h v o h 1 v o h 1 v i l v i l v i l v i l v i l v i l v i l v i l v o l 1 v o l 1 t a s t a h p w l w , p w l r p w h w , p w h r t c y c w , t c y c r t w r f t w r r t d s w t h t d d r t d h r r s c s b w r b r d b s e e n o t e 2 ) d b 0 ~ d b 1 7 s e e n o t e 2 ) d b 0 ~ d b 1 7 s e e n o t e 1 ) n o t e 1 ) p w l w a n d p w l r a r e d e f i n e d b y t h e o v e r l a p p e r i o d w h e n c s b i s l o w a n d w r b o r r d d i s l o w . n o t e 2 ) u n u s e d d b p i n s m u s t b e f i x e d a t i o v c c o r g n d . w r i t e d a t a r e a d d a t a
LG4572B ver. 1.0. 4 lge confidential 262 8 reference applications 8.1 configuration of power su pply circuit figure 118 is one of the configurations of power supply circuits to generate liquid crystal panel drive levels.
LG4572B ver. 1.0. 4 lge confidential 263 figure 118 . one example of applica tion circuits for the stmode=7 case. some application circuitries in the above power supply circuit configuration should be changed according to the below setting modes. please see the followings. v d d v d d o u t c 3 1 n c 3 1 p v d d r e g u l a t o r c b 8 s t e p 3 s o u r c e d r i v e r s < 1 : 1 4 4 0 > c 2 1 p c 2 1 n c 2 1 c 2 2 d d v d h s t e p 2 c b 2 c 2 2 p c 2 2 n v c l c 2 3 c 2 3 p c 2 3 n v g h c b 3 d 2 v g l c b 1 l s w p f m b o o s t r e g u l a t o r v r e g 1 o u t c b 1 1 v r e g 2 o u t c b 1 0 d d v d l i n t e r n a l o s c l o g i c v c o m v c i c 2 4 c 2 4 p c 2 4 n d d v d h l v g l g a t e l e v e l s h i f t e r d 1 v c i d 4 m 1 c b 7 d 6 d 5 l 1 c b v c b p v c b n l g 4 5 7 2 v g l c b 5 o s c 1 o s c 2 o s c 3 b l u _ e n c 4 1 n c 4 1 p s t e p 4 f w _ l , b w _ l , g p w r 1 _ l , g p w r 2 _ l , g c l k 1 ~ 4 _ l , g v s t 1 , 2 _ l , f w _ r , b w _ r , g p w r 1 _ r , g p w r 2 _ r , g c l k 1 ~ 4 _ r , g v s t 1 ~ 2 _ r c r e g c b 1 2 b l u _ p w m c c 1 c c 2 r c 1 o n l y f o r m i p i o p t i o n a l
LG4572B ver. 1.0. 4 lge confidential 264 stmode[2:0] = 6 (pfm C step - up 3) stmode[2:0] = 7 (pfm C di ode inverting) under some abnormal situations, such as no power - on reset in the system or as un - kept power on/off sequences or as something else , external mos switch should be protected by inse rting high pass filter between lsw and mos gate node of n1 in the following figure . the hpf circuits in the following figure is a recommended one. the connection of 1uf capacitance near to inductor and/or mos switch could help to reduce the noises from vci power node. but they are al l optionals for special cases. figure 119 . hpf (high pass filter) application circuits for protecting external mos tr. specification of external elements connected to lg 4572b power supply the follow ing table s show specifications of external element connected to the lg 4572b ?s power supply circuit. c 3 1 n c 3 1 p s t e p 3 l s w p f m b o o s t d d v d l d d v d h v c i d 4 m 1 c b 7 d 6 l 1 v c b p c 3 1 c b 5 c 3 1 n c 3 1 p s t e p 3 l s w p f m b o o s t d d v d l d d v d h v c i d 4 m 1 c b 7 d 6 d 5 l 1 c b v c b p v c b n c b 5 v c i l s w t h e d c c u r r e n t u n d e r a b n o r m a l s i t u a t i o n s , w h i c h c a n c a u s e t h e r m a l h e a t i n g s o f m o s o r i n d u c t o r , c a n b e p r e v e n t e d b y u s i n g h i g h p a s s f i l t e r b e t w e e n l s w a n d m o s g a t e ( n 1 ) . 1 n f 1 0 k n 1 s c h o t t k y 1 u f t h i s 1 u f f o r v c i c a n b e m o r e e f f e c t i v e i f i t i s a s c l o s e t o p f m c o m p o n e n t s . h p f
LG4572B ver. 1.0. 4 lge confidential 265 table 34 . capacitor capacity recommended voltage pin connection 1uf (b characteristics) 6v c24, cb3, cb10**, cb11**, cb12 10v c21, c22, c23, c31* 25v cb1, cb2 1.0 uf 10v cb5, cb7 1.0 uf 6v cb8 0.47uf 10v cb* note: some components* are optional according to the specific usages and some compon en ts** would be eliminated after reliability test. table 35 . resistor resistor value recommended voltage pin connection 10k c1 * ( < 1% error tolerant resistor) n ote: some components* are optional according to the specific usages and some componts** would be eliminated after reliability test . table 36 . schottky diode feature pin connection vf < 0.4v/20ma at 25c , vr>30v d1**, d2, d4, d5*, d6** note: some components* are optional according to the specific usages and some compon en ts** would be eliminated after reliability test. table 37 . n - ch mosfet feature speci fication m1 idss<1a at vds>16v, vgs=0v, and 25 c ron<1.25 at vgs=2.5v and id=300ma ton<30ns(typ.) toff<30ns(typ.) note: recommended n - ch mosfets : 1. si1012r/x (vishay siliconix) 2. rum003n02 (rohm) table 38 . inductor for booster feature inductance specification l1 inductance value = 4.7uh inductance tolerance < 20% dc resistance ( 30%) < 0.24ohm max. rated current > 145ma at saturation max. rated current > 470ma at temperature rise note: recommended inductor components :
LG4572B ver. 1.0. 4 lge confidential 266 1. cbmf1608t4r7m (taiyo yuden) 2. vlf3010at - 4r7mr70 (tdk)
LG4572B ver. 1.0. 4 lge confidential 267 9 histor y of revision ver . date note 1.0.0 2010.04.12 - pin descriptions are modified from page 7 - 8 in red colors. - 5.2.4 revived. - fh function is revived in page 150 and 152. - type error is fixed in page 162 regarding ten. - descriptions are updated in pag e 165. 1.0.1 2010.05.06 - cabc function descriptions are updated in 5.8 - some comments on iovcc in page 9 are deleted to avoid unnecessary misunderstanding. 1.0.2 2010.0 7 . 08 - description on a1h register is added in page 176. - default setting value for lpm is fixed in page 231. - typo max. allowable setting values for vgh and vgl/lvgl are fixed in page 82. - mddi 18bit interface is not supported anymore in page 67 - 69. 1.0.3 2010.09.14 - typo is fixed in page 204, where osc sync enabled or disabled settings are exchanged. 1.0.4 2011.04.01 - errors in timing tables from p.183 to p.194 are corrected, which are sdt, shpn, engnd, clw, gno, fti, and gpm parameters when rc - osc frequencies are used for them.

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